文件列表:

code (0, 2007-02-26)
code\capsense.v (6918, 2006-12-26)
doc (0, 2007-02-26)
doc\Auto_Start.pdf (198434, 2007-02-22)
modelsim (0, 2007-02-26)
modelsim\capsense.v (6918, 2006-12-26)
modelsim\capsense_sim.cr.mti (898, 2006-12-29)
modelsim\capsense_sim.mpf (9998, 2006-12-29)
modelsim\test_capsense.v (3006, 2006-12-29)
modelsim\wave.bmp (342178, 2006-12-29)
modelsim\wave.do (1512, 2006-12-29)
modelsim\work (0, 2007-02-26)
modelsim\work\altufm_osc0_altufm_osc_1p3 (0, 2007-02-26)
modelsim\work\altufm_osc0_altufm_osc_1p3\verilog.psm (6795, 2006-12-29)
modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.dat (862, 2006-12-29)
modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.vhd (214, 2006-12-29)
modelsim\work\capsense (0, 2007-02-26)
modelsim\work\capsense\verilog.psm (5006, 2006-12-29)
modelsim\work\capsense\_primary.dat (662, 2006-12-29)
modelsim\work\capsense\_primary.vhd (436, 2006-12-29)
modelsim\work\counter (0, 2007-02-26)
modelsim\work\counter\verilog.psm (7523, 2006-12-29)
modelsim\work\counter\_primary.dat (716, 2006-12-29)
modelsim\work\counter\_primary.vhd (305, 2006-12-29)
modelsim\work\nxt_state (0, 2007-02-26)
modelsim\work\nxt_state\verilog.psm (5811, 2006-12-29)
modelsim\work\nxt_state\_primary.dat (530, 2006-12-29)
modelsim\work\nxt_state\_primary.vhd (352, 2006-12-29)
modelsim\work\read (0, 2007-02-26)
modelsim\work\read\verilog.psm (7440, 2006-12-29)
modelsim\work\read\_primary.dat (461, 2006-12-29)
modelsim\work\read\_primary.vhd (514, 2006-12-29)
modelsim\work\test_capsense (0, 2007-02-26)
modelsim\work\test_capsense\verilog.psm (16965, 2006-12-29)
modelsim\work\test_capsense\_primary.dat (1742, 2006-12-29)
modelsim\work\test_capsense\_primary.vhd (86, 2006-12-29)
modelsim\work\write (0, 2007-02-26)
modelsim\work\write\verilog.psm (2471, 2006-12-29)
modelsim\work\write\_primary.dat (236, 2006-12-29)
... ...

Autostart with capsense Design Resource usage Total LEs used: 45 (19% on EPM 240) Pin assignment & any special notes: No. of ports used for this demo: 8 cap_a: pin 83 cap_b: pin 84 led1: pin 69 led2: pin 70 led3: pin 71 led4: pin 72 pwr_dwn: pin 14 pwr_dwn_inv: pin 12 Special notes: Unused pins *MUST* be assigned as 'Input Tristated' If Autostart or LEDblink design were running previously on the board, keep SW4 pressed while beginning programming of this program. After programming you *MUST* remove the JTAG programming cable for this design to work. Demo notes: * Select VCCIO1 as 1.8V (JP9) * Select VCCIO2 as 2.775V (JP7) * Switch On SW1 (power) and observe VCCINT and VCCIOs being powered down and powered up cyclically. * Also observe the 4 LEDs (D2, D3, D5, D6) shift their position each time the power to CPLD is restored - Each time the LED blinks, its position is based upon previous LED position that blinked

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