dpll
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：4KB
下载次数：461
上传日期：2008-05-23 18:41:18
上 传 者：
WINYP
说明： ＦＰＧＡ实现全数字锁相环，利用硬件描述评议verilog HDL，顶层文件ＤＰＬＬ．Ｖ
(FPGA realization of all-digital phase-locked loop, using hardware description Convocation verilog HDL, the top-level document DPLL. V)
文件列表:
dpll\divfrequency32.v (398, 2008-03-21)
dpll\divfrequency32_tp.v (264, 2008-03-20)
dpll\divfrequency64.v (429, 2008-03-21)
dpll\divfrequency64_tp.v (266, 2008-03-20)
dpll\divfrequency8.v (364, 2008-03-21)
dpll\divfrequency8_tp.v (275, 2008-03-20)
dpll\dpll.v (1520, 2008-03-21)
dpll\dpll_tp.v (375, 2008-03-27)
dpll\maichongjiajian.v (3292, 2008-03-20)
dpll\maichongjiajian_tp.v (385, 2008-03-20)
dpll\moKcounter.v (2253, 2008-03-21)
dpll\moKcounter_tp.v (385, 2008-03-20)
dpll\xorphd.v (161, 2008-03-21)
dpll\xorphd_tp.v (249, 2008-03-21)
dpll (0, 2008-05-05)
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