FIR
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：5KB
下载次数：128
上传日期：2008-05-23 18:43:59
上 传 者：
WINYP
说明： ＦＰＧＡ实现数字滤波器，基于硬件描述语言ＶＥＲＩＬＯＧ ＨＤＬ，顶层文件ＦＩＲ．Ｖ
(FPGA realization of digital filters, based on the hardware description language VERILOG HDL, the top-level file FIR. V)
文件列表:
FIR\add3.v (113, 2008-04-27)
FIR\adder16.v (472, 2008-04-23)
FIR\adder4.v (662, 2008-04-22)
FIR\adder8.v (475, 2008-04-23)
FIR\adderbu.v (244, 2008-04-25)
FIR\alu.v (623, 2008-04-24)
FIR\boothcode.v (1174, 2008-04-27)
FIR\fir.v (1493, 2008-04-27)
FIR\fir_control.v (829, 2008-04-25)
FIR\fir_tp.v (963, 2008-04-27)
FIR\mux16_2.v (785, 2008-04-23)
FIR\mux8_1.v (462, 2008-04-24)
FIR\shift.v (779, 2008-04-26)
FIR\trigger1.v (269, 2008-04-25)
FIR\trigger2.v (175, 2008-04-27)
FIR\wallace.v (2279, 2008-04-27)
FIR (0, 2008-04-27)
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