clock
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：227KB
下载次数：217
上传日期：2008-05-26 18:58:45
上 传 者：
borise123
说明： 数字钟的程序，功能说明如下所示：
1.完成秒／分／时的依次显示并正确计数；
2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位；
3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时；
4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整
5.可以选择使用12进制计时或者24进制计时。
使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。
(Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.)
文件列表:
clock\Block1.bdf (10922, 2008-03-08)
clock\db\REL_clock.(0).cnf.cdb (11327, 2008-04-11)
clock\db\REL_clock.(0).cnf.hdb (1328, 2008-04-11)
clock\db\REL_clock.analyze_file.qmsg (1594, 2008-03-08)
clock\db\REL_clock.asm.qmsg (1614, 2008-04-16)
clock\db\REL_clock.cbx.xml (91, 2008-04-16)
clock\db\REL_clock.cmp.cdb (22535, 2008-04-16)
clock\db\REL_clock.cmp.hdb (7006, 2008-04-16)
clock\db\REL_clock.cmp.kpt (209, 2008-04-16)
clock\db\REL_clock.cmp.logdb (4, 2008-04-16)
clock\db\REL_clock.cmp.rdb (22086, 2008-04-16)
clock\db\REL_clock.cmp.tdb (14573, 2008-04-16)
clock\db\REL_clock.cmp0.ddb (30930, 2008-04-16)
clock\db\REL_clock.dbp (0, 2008-04-16)
clock\db\REL_clock.db_info (136, 2008-03-08)
clock\db\REL_clock.eco.cdb (141, 2008-05-26)
clock\db\REL_clock.eds_overflow (4, 2008-04-16)
clock\db\REL_clock.fit.qmsg (38658, 2008-04-16)
clock\db\REL_clock.hier_info (4590, 2008-04-16)
clock\db\REL_clock.hif (584, 2008-04-16)
clock\db\REL_clock.map.cdb (6294, 2008-04-16)
clock\db\REL_clock.map.hdb (6860, 2008-04-16)
clock\db\REL_clock.map.logdb (4, 2008-04-16)
clock\db\REL_clock.map.qmsg (3840, 2008-04-16)
clock\db\REL_clock.pre_map.cdb (6992, 2008-04-16)
clock\db\REL_clock.pre_map.hdb (7651, 2008-04-16)
clock\db\REL_clock.psp (0, 2008-04-16)
clock\db\REL_clock.rtlv.hdb (7641, 2008-04-16)
clock\db\REL_clock.rtlv_sg.cdb (6937, 2008-04-16)
clock\db\REL_clock.rtlv_sg_swap.cdb (158, 2008-04-16)
clock\db\REL_clock.sgdiff.cdb (5775, 2008-04-16)
clock\db\REL_clock.sgdiff.hdb (7730, 2008-04-16)
clock\db\REL_clock.signalprobe.cdb (488, 2008-04-16)
clock\db\REL_clock.sim.hdb (2369, 2008-05-26)
clock\db\REL_clock.sim.qmsg (3157, 2008-05-26)
clock\db\REL_clock.sim.rdb (3530, 2008-05-26)
clock\db\REL_clock.sim.vwf (20247, 2008-05-26)
clock\db\REL_clock.sld_design_entry.sci (134, 2008-05-26)
clock\db\REL_clock.sld_design_entry_dsc.sci (134, 2008-04-16)
clock\db\REL_clock.syn_hier_info (0, 2008-04-16)
... ...
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