Verilog_example
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1040KB
下载次数：92
上传日期：2008-05-28 17:16:32
上 传 者：
qiutingyun
说明： 本文件包括多路选择器器建模，译码器实验程序，加法器实验程序，比较器实验程序，计数器建模，I2C接口标准建模源码，串行接口RS232标准建模源码标准，LCM建模源码，时钟６分频源码，串并转化源码。
，对于硬件设计初学者来说有一定的参考价值。
(This document includes MUX device modeling, experimental procedure decoder, adder experimental procedures, experimental procedures comparators, counters modeling, I2C interface standard modeling source, standard RS232 serial interface modeling source standards, LCM modeling source, clock frequency source 6, and transforming source string. For hardware design beginners have a certain reference value.)
文件列表:
Verilog源码例子\6分频\G5f.v (369, 2006-06-05)
Verilog源码例子\6分频\tb_g5f.v (193, 2006-06-05)
Verilog源码例子\6分频 (0, 2008-05-28)
Verilog源码例子\adder\ise\adder\.untf (0, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.bgn (5138, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.bit (167051, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.bld (767, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.cmd_log (679, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.dhp (991, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.drc (38, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.lfp (641, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.lso (6, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.mrp (7135, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.nc1 (37, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.ncd (2989, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.ngc (3937, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.ngd (6436, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.ngm (13808, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.ngr (2201, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.npl (519, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.pad (8021, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.pad_txt (31272, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.par (3390, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.pcf (687, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.placed_ncd_tracker (0, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.prj (22, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.routed_ncd_tracker (0, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.stx (0, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.syr (8479, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.twr (2607, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.twx (15587, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.ucf (606, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.ucf.untf (0, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.ut (518, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.v (643, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder.xpi (46, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder_map.ncd (1918, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder_map.ngm (13808, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder_pad.csv (8025, 2006-02-24)
Verilog源码例子\adder\ise\adder\adder_pad.txt (31272, 2006-02-24)
... ...
近期下载者：
相关文件：
收藏者：