CPU

所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:42KB
下载次数:247
上传日期:2008-06-02 16:34:00
上 传 者haotianr
说明:  使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个通用寄存器、一个程序计数器PC、一个标志寄存器FLAG,一个堆栈寄存器STACK。存储器寻址粒度为字节。数据存储以32位字对准。采用32位定长指令格式,采用Load/Store结构,ALU指令采用三地址格式。支持有符号和无符号整数加、减、乘、除运算,并支持浮点数加、减、乘、除四种运算,支持与、或、异或、非4种逻辑运算,支持逻辑左移、逻辑右移、算术右移、循环右移4种移位运算,支持Load/Store操作,支持地址/立即数加载操作,支持无条件转移和为0转移、非0转移、无符号>转移、无符号<转移、有符号>转移、有符号<转移等条件转移。

文件列表:
add.v (3788, 2007-12-27)
alu.v (11426, 2007-12-22)
condcontrol.v (1803, 2007-12-19)
control.v (6001, 2008-01-02)
d_8.v (7025, 2007-12-22)
d_8_1.v (7001, 2008-01-01)
d_8_1_bb.v (5605, 2008-01-01)
d_8_bb.v (5612, 2007-12-22)
d_32.v (6506, 2007-12-19)
d_32_bb.v (5193, 2007-12-19)
d_32_inst.v (134, 2007-12-19)
datapath.v (8313, 2008-01-20)
div.v (1183, 2008-01-02)
fpu_arch.v (726, 2008-01-02)
func_lib.v (6674, 2007-12-19)
in_32.v (6661, 2007-12-19)
in_32_bb.v (5289, 2007-12-19)
in_32_inst.v (136, 2007-12-19)
instruction_32.v (6745, 2007-12-20)
instruction_32_1.v (7274, 2008-01-01)
instruction_32_1_bb.v (5815, 2008-01-01)
instruction_32_bb.v (5367, 2007-12-20)
instruction_32_inst.v (154, 2007-12-20)
mul.v (1109, 2008-01-02)
pc.v (344, 2007-12-19)
regfile.v (6199, 2007-12-19)
ss.v (7261, 2007-12-20)
ss_bb.v (5835, 2007-12-20)
ss_syn.v (22932, 2007-12-20)
stack.v (794, 2007-12-20)
sub.v (222, 2007-12-27)

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