sin
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2470KB
下载次数：268
上传日期：2008-06-07 22:15:55
上 传 者：
dahuoji
说明： 正弦信号发生器程序,用VERILOG写出。
(Sinusoidal signal generator procedures, used to write Verilog.)
文件列表:
正弦信号发生器\_ODELSIM\ROM.V (5884, 2006-01-13)
正弦信号发生器\_ODELSIM\SIN_TOP.MPF (22370, 2006-06-28)
正弦信号发生器\_ODELSIM\SIN_TOP.V (1593, 2006-06-16)
正弦信号发生器\_ODELSIM\VSIM.WLF (106496, 2006-06-28)
正弦信号发生器\_ODELSIM\sin_top.cr.mti (6654, 2006-06-28)
正弦信号发生器\_ODELSIM\sin_top_TB.v (1109, 2006-06-28)
正弦信号发生器\_ODELSIM\dataHEX\SDATA.ASM (447, 2004-12-02)
正弦信号发生器\_ODELSIM\dataHEX\SDATA.BIN (64, 2004-12-02)
正弦信号发生器\_ODELSIM\dataHEX\SDATA.HEX (168, 2004-12-02)
正弦信号发生器\_ODELSIM\dataHEX\SDATA.LST (6213, 2004-12-02)
正弦信号发生器\_ODELSIM\WORK\_INFO (30332, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratixgx_dpa_lvds_rx\VERILOG.ASM (117251, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratixgx_dpa_lvds_rx\_PRIMARY.DAT (7618, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratixgx_dpa_lvds_rx\_PRIMARY.VHD (799, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_rublock\VERILOG.ASM (34129, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_rublock\_PRIMARY.DAT (3803, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_rublock\_PRIMARY.VHD (770, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_register\VERILOG.ASM (91966, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_register\_PRIMARY.DAT (18376, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_register\_PRIMARY.VHD (912, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_internal\VERILOG.ASM (1155866, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_internal\_PRIMARY.DAT (29631, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_internal\_PRIMARY.VHD (2111, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_clear\VERILOG.ASM (5054, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_clear\_PRIMARY.DAT (607, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_clear\_PRIMARY.VHD (368, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_block\VERILOG.ASM (147898, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_block\_PRIMARY.DAT (16283, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_ram_block\_PRIMARY.VHD (3750, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_pll\VERILOG.ASM (741266, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_pll\_PRIMARY.DAT (71502, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_pll\_PRIMARY.VHD (8543, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_mac_register\VERILOG.ASM (47269, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_mac_register\_PRIMARY.DAT (9356, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_mac_register\_PRIMARY.VHD (557, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_mac_out_internal\VERILOG.ASM (91272, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_mac_out_internal\_PRIMARY.DAT (8998, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_mac_out_internal\_PRIMARY.VHD (1036, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_mac_out\VERILOG.ASM (84693, 2006-06-28)
正弦信号发生器\_ODELSIM\WORK\stratix_mac_out\_PRIMARY.DAT (7531, 2006-06-28)
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