文件列表:

AD9244 ADC + AD9744 DAC (C) (0, 2021-03-16)
** (2582, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\ADC_DAC.dpj (3867, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\adc_dac.ldf (20946, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\adc_dac_for_extendercard.dpg (785, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core A (0, 2021-03-16)
AD9244 ADC + AD9744 DAC (C)\Core A\ADV7179_reset.c (848, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core A\ADV7183_reset.c (1406, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core A\CoreA.dpj (5856, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core A\Interrupt_Init.c (572, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core A\Interrupt_Service.c (640, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core A\main.c (1752, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core A\main.h (1527, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core A\PPI0_Init.c (1298, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core B (0, 2021-03-16)
AD9244 ADC + AD9744 DAC (C)\Core B\CoreB.dpj (5274, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core B\Interrupt_Init.c (572, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core B\Interrupt_Service.c (503, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core B\main.c (1828, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core B\main.h (1501, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Core B\PPI1_Init.c (1923, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\dummy.c (132, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Init_SDRAM.c (585, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\set_PLL.c (2051, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Shared Memory L2 (0, 2021-03-16)
AD9244 ADC + AD9744 DAC (C)\Shared Memory L2\L2_SRAM.c (239, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Shared Memory L2\L2_SRAM.dpj (2899, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Shared Memory L2\L2_SRAM.h (497, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Shared Memory L3 (0, 2021-03-16)
AD9244 ADC + AD9744 DAC (C)\Shared Memory L3\L3_SDRAM.c (392, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Shared Memory L3\L3_SDRAM.dpj (2902, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\Shared Memory L3\L3_SDRAM.h (554, 2006-05-26)
AD9244 ADC + AD9744 DAC (C)\system.h (1675, 2006-05-26)
Audio Codec Talkthrough - TDM (C) (0, 2013-01-21)
Audio Codec Talkthrough - TDM (C)\CoreA.dpj (4553, 2008-01-02)
Audio Codec Talkthrough - TDM (C)\CoreB.dpj (2770, 2008-01-02)
Audio Codec Talkthrough - TDM (C)\dummy.c (27, 2008-01-02)
Audio Codec Talkthrough - TDM (C)\Initialize.c (5108, 2008-01-02)
Audio Codec Talkthrough - TDM (C)\ISR.c (1626, 2008-01-02)
... ...

**************************************************************************************************** ADSP-BF561 EZ-KIT Video TalkThrough Example Analog Devices, Inc. DSP Division Three Technology Way Norwood, MA 02062 Date Created: 11/11/03 Change History: 04/30/04 : eliminated silicon revision check example now works for rev 0.2 and higher ____________________________________________________________________________________________________ This example streams input from a video source to a output screen. A video source is aquired frame-by-frame into SDRAM from the VideoDecoder. The frames are then output with a one-frame delay to the Encoder. In this example, no processing is done on the frames. They are passed unaltered. This is a dual core project. Please see section III. to get familiar with the project structure ____________________________________________________________________________________________________ Requires ADSP-BF561 silicon revision of 0.2 or higher ____________________________________________________________________________________________________ CONTENTS I. FUNCTIONAL DESCRIPTION II. OPERATION DESCRIPTION III. PROJECT STRUCTURE I. FUNCTIONAL DESCRIPTION Core A sets up Clock frequencies, SDRAM controller, the Video Encoder and Decoder, and PPI0 to perform the video acquisiton in ITU-656 mode. Frames are stroed in SDRAM (in a circular fashion, 4 frames at a time). Core B sets up PPI1 to perform video output. It then waits for the first valid frame in memory from Core A, and starts the transfers. GP output mode is used. Both the Video Encoder and Decoder are kept in their power on configuration, no other configuration is done. If you need to change settings, you may do so by adding code for I2C routines. II. OPERATION DESCRIPTION - Open the project group "video_in_out.dpg" in the VisualDSP Integrated Development Environment (IDDE). Follow instructions in section III. - Under the "Project" tab, select "Build Project" (program is then loaded automatically into DSP). - Connect a video NTSC/PAL CVBS source to the bottom right connector of J6 (video in/out jack) - Connect a video display monitor to the video output jack (top middle connector of J6) - Dipswitch SW5: set #1 to "off", all others to on - Dipswitch SW2: set #2,3,5 to "off", #1,4,6 to on - Dipswitch SW3: set #1,4 to "off", #2,3 to on - Run the executables by pressing "multiprocessor run" (CTRL-F5) on the toolbar. DO NOT use the single core (F5) button. You should see a copy of the input video in the output screen. - Halt the processor ("multiprocessor halt" button). If you open a memory window and go to the addresses of _sFrame0,1,2,3, you see the video data of the four frames. - The main header file "system.h" contains #define statements for most of the system settings (clock frequencies etc) III. PROJECT STRUCTURE This is a dual core project. It consists of a main project - containing only system defines and linker settings- ".\video_in_out.dpj", four sub-projects - containing the source code - ".\coreA\coreA.dpj" ( code exclusive to core A, in L1 memory) ".\coreB\coreB.dpj" ( code exclusive to core B, in L1 memory) ".\Shared Memory L2\L2_SRAM.dpj" ( code that is shared between the cores, in on-chip L2 memory) ".\Shared Memory L3\L3_SDRAM.dpj" ( code that is shared between the cores, in off-chip L3 memory, SDRAM), and the project group file that ties everything together ".\video_in_out.dpj". Follow this procedure to open and compile the project: - open the project group (File-> Open-> Project Group) - right click on the main projectand re-build the project.

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