ARelativelySimpleRISCCPU
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：219KB
下载次数：91
上传日期：2008-06-25 09:21:08
上 传 者：
ulin2018
说明： A Relatively Simple RISC CPU 设计源码并附详细的说明文档。可以ModelSim进行仿真，并可以用synplify进行综合。
(A Relatively Simple RISC CPU design source with detailed documentation. ModelSim simulation can be carried out, and they can Synplify synthesis.)
文件列表:
ARelativelySimpleRISCCPU\risc_cpu\cpu_top.v (1730, 2008-06-03)
ARelativelySimpleRISCCPU\risc_cpu\counter.v (307, 2008-05-16)
ARelativelySimpleRISCCPU\risc_cpu\machine.v (5652, 2008-06-03)
ARelativelySimpleRISCCPU\risc_cpu\machinectl.v (205, 2008-06-03)
ARelativelySimpleRISCCPU\risc_cpu\ram.v (267, 2008-06-03)
ARelativelySimpleRISCCPU\risc_cpu\register.v (1031, 2008-06-03)
ARelativelySimpleRISCCPU\risc_cpu\rom.v (217, 2008-05-16)
ARelativelySimpleRISCCPU\risc_cpu\ datactl.v (143, 2008-05-16)
ARelativelySimpleRISCCPU\risc_cpu\accum.v (308, 2008-06-03)
ARelativelySimpleRISCCPU\risc_cpu\addr_decode.v (390, 2008-05-16)
ARelativelySimpleRISCCPU\risc_cpu\adr.v (161, 2008-05-16)
ARelativelySimpleRISCCPU\risc_cpu\alu.v (800, 2008-06-03)
ARelativelySimpleRISCCPU\risc_cpu\clk_gen.v (2534, 2008-05-16)
ARelativelySimpleRISCCPU\risc_cpu\test_cpu.v (843, 2008-06-03)
ARelativelySimpleRISCCPU\risc_cpu\datactl.v (143, 2008-05-16)
ARelativelySimpleRISCCPU\risc_cpu\Risc_cpu设计说明文档.doc (783360, 2008-06-25)
ARelativelySimpleRISCCPU\risc_cpu (0, 2008-06-25)
ARelativelySimpleRISCCPU (0, 2008-06-25)
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