clock

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:320KB
下载次数:45
上传日期:2008-06-26 21:15:27
上 传 者lgcoollgcool
说明:  自己编写的一个verilog时钟程序,在xilinx的ISE仿真通过
(I have written a Verilog clock procedures, in Xilinx s ISE simulation through)

文件列表:
clock\clock.ise (247311, 2000-06-19)
clock\__ISE_repository_clock.ise_.lock (151, 2000-06-19)
clock\clock_test.xwv (19764, 2000-06-18)
clock\clock_test.tfw (1698, 2000-06-18)
clock\clock_test.ant (4933, 2000-06-18)
clock\clock_test.jhd (50, 2000-06-18)
clock\xilinxsim.ini (21, 2000-06-18)
clock\isim.log (1674, 2000-06-18)
clock\clock.ise_ISE_Backup (247311, 2000-06-19)
clock\clock_test_isim_beh.exe (226668, 2000-06-18)
clock\isim.hdlsourcefiles (82, 2000-06-18)
clock\clock2_test.v (1452, 2000-06-18)
clock\clock2_test_v_stx.prj (114, 2000-06-18)
clock\clock2_test_bencher.prj (67, 2000-06-18)
clock\clock2_test.xwv (21564, 2000-06-18)
clock\clock2_test.xwv_bak (21564, 2000-06-18)
clock\clock2_test.tfw (2214, 2000-06-18)
clock\clock2_test.ant (5454, 2000-06-18)
clock\clock2_test.tbw (845, 2000-06-18)
clock\clock2_test.jhd (51, 2000-06-18)
clock\clock2_test_beh.prj (101, 2000-06-18)
clock\clock2_test_isim_beh.exe (233858, 2000-06-18)
clock\tmpRTVStore.xwv (21564, 2000-06-18)
clock\clock.v (5294, 2000-06-18)
clock\clock_summary.html (2278, 2000-06-19)
clock\clock_stx.prj (79, 2000-06-18)
clock\clock_test_bencher.prj (67, 2000-06-18)
clock\clock_test.xwv_bak (19764, 2000-06-18)
clock\clock_test.tbw (919, 2000-06-18)
clock\clock_test_beh.prj (100, 2000-06-18)
clock\isim.cmd (14, 2000-06-18)
clock\isimwavedata.xwv (20716, 2000-06-18)
clock\isim.tmp_save\_1 (4729, 2000-06-18)
clock\isim\work\hdllib.ref (293, 2000-06-18)
clock\isim\work\hdpdeps.ref (432, 2000-06-18)
clock\isim\work\clock2__test\clock2__test.h (1180, 2000-06-18)
clock\isim\work\clock2__test\xsimclock2__test.cpp (2241, 2000-06-18)
clock\isim\work\clock2__test\mingw\clock2__test.obj (36499, 2000-06-18)
clock\isim\work\vlg1D\clock2__test.bin (4978, 2000-06-18)
clock\isim\work\glbl\glbl.h (946, 2000-06-18)
... ...

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