sd_IP
所属分类：其他
开发工具：VHDL
文件大小：8KB
下载次数：240
上传日期：2008-06-27 16:05:28
上 传 者：
scorpion1025
说明： SD card controller can just read data using 1 bit SD mode.
I have written this core for NIOS2 CPU, Cyclone, but I think it can works
with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and
CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.
Good luck
(SD card controller can just read data using 1 bit SD mode.I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.Good luck)
文件列表:
sd卡读写IP\sd\class.ptf (4699, 2005-07-07)
sd卡读写IP\sd\crc_unit_16.v (796, 2006-07-28)
sd卡读写IP\sd\crc_unit_7.v (1009, 2006-07-28)
sd卡读写IP\sd\inc\altera_avalon_camelot_sd_controller_regs.h (423, 2005-07-07)
sd卡读写IP\sd\inc (0, 2008-05-06)
sd卡读写IP\sd\mk_user_logic_Camelot_SD_Controller.pl (499, 2005-07-07)
sd卡读写IP\sd\sd.v (1975, 2006-07-28)
sd卡读写IP\sd\sd_controller.v (9661, 2006-07-28)
sd卡读写IP\sd\sd_host.v (4333, 2006-07-28)
sd卡读写IP\sd\soft example for nios2\main.cpp (1407, 2006-07-18)
sd卡读写IP\sd\soft example for nios2 (0, 2008-05-06)
sd卡读写IP\sd (0, 2008-05-06)
sd卡读写IP (0, 2008-05-06)
Written by Vladimir Boykov (vboykov@yandex.ru),
Verilog, last modification August, 2005.
Just for free use not for selling.
SD card controller can just read data using 1 bit SD mode.
I have written this core for NIOS2 CPU, Cyclone, but I think it can works
with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and
CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.
Good luck!!!
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