RISC_Core
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：309KB
下载次数：44
上传日期：2008-06-30 20:33:31
上 传 者：
fenglinhuoshan
说明： 这是用VerilogHDL描述的一个8位精简指令集处理器，包含完整代码，各种文档，以及测试环境。
(This is described in VerilogHDL with an 8-bit RISC processor, including the integrity of the code, a variety of documents, as well as the test environment.)
文件列表:
RISC Core\verilog\doc\risc8.pdf (127850, 2000-02-09)
RISC Core\verilog\doc\risc8.ps (172097, 2000-02-09)
RISC Core\verilog\doc (0, 2000-09-05)
RISC Core\verilog\src\risc8.v (8232, 2000-02-09)
RISC Core\verilog\src\risc8_alu.v (8411, 2000-02-09)
RISC Core\verilog\src\rbcla_adder.v (3145, 2000-02-09)
RISC Core\verilog\src\risc8_control.v (30664, 2000-02-09)
RISC Core\verilog\src\risc8_regb_biu.v (14294, 2000-02-09)
RISC Core\verilog\src\risc8_constants.v (7970, 2000-02-09)
RISC Core\verilog\src\risc8_parameters.v (969, 2000-02-09)
RISC Core\verilog\src (0, 2000-09-05)
RISC Core\verilog\sim\compile (293, 2000-02-09)
RISC Core\verilog\sim\regression (2613, 2000-02-09)
RISC Core\verilog\sim\test.v (5075, 2000-02-09)
RISC Core\verilog\sim\run_interac (274, 2000-02-09)
RISC Core\verilog\sim\test.mem (517, 2000-02-09)
RISC Core\verilog\sim\risc8.cfg (6166, 2000-02-09)
RISC Core\verilog\sim\reg.mem (44, 2000-02-09)
RISC Core\verilog\sim\run_batch (277, 2000-02-09)
RISC Core\verilog\sim\DW01_add.v (516, 2000-02-09)
RISC Core\verilog\sim\asm\and.mem (479, 2000-02-09)
RISC Core\verilog\sim\asm\and.asm (1288, 2000-02-09)
RISC Core\verilog\sim\asm\arith.mem (1520, 2000-02-09)
RISC Core\verilog\sim\asm\or.asm (1245, 2000-02-09)
RISC Core\verilog\sim\asm\arith.asm (3845, 2000-02-09)
RISC Core\verilog\sim\asm\jmp.mem (800, 2000-02-09)
RISC Core\verilog\sim\asm\loadstore.asm (1734, 2000-02-09)
RISC Core\verilog\sim\asm\logic.mem (582, 2000-02-09)
RISC Core\verilog\sim\asm\or.mem (461, 2000-02-09)
RISC Core\verilog\sim\asm\moves.asm (1433, 2000-02-09)
RISC Core\verilog\sim\asm\divide.mem (679, 2000-02-09)
RISC Core\verilog\sim\asm\moves.mem (517, 2000-02-09)
RISC Core\verilog\sim\asm\waitstates.asm (1215, 2000-02-09)
RISC Core\verilog\sim\asm\assemble_all (101, 2000-02-09)
RISC Core\verilog\sim\asm\interrupt.asm (2392, 2000-02-09)
RISC Core\verilog\sim\asm\interrupt.mem (702, 2000-02-09)
RISC Core\verilog\sim\asm\logic.asm (1542, 2000-02-09)
RISC Core\verilog\sim\asm\jmp.asm (2301, 2000-02-09)
RISC Core\verilog\sim\asm\flags.asm (5653, 2000-02-09)
RISC Core\verilog\sim\asm\divide.asm (1562, 2000-02-09)
... ...
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