文件列表:

xapp485 (0, 2008-05-06)
xapp485\4bit_constraints (0, 2008-05-06)
xapp485\4bit_constraints\Copy of top4_rx_3s500e_fg320_tl_a.ucf (982, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s100e_cp132_t_a.ucf (1538, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s100e_vq100_t_a.ucf (1572, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s1200e_fg320_tl_a.ucf (1333, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s1200e_fg320_tr_a.ucf (1343, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s1200e_ft256_tl_a.ucf (1538, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s1200e_ft256_tr_a.ucf (1530, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s1600e_fg320_tl_a.ucf (1333, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s1600e_fg320_tr_a.ucf (1343, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s1600e_fg484_tl_a.ucf (1305, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s250e_cp132_t_a.ucf (1537, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s250e_ft256_tl_a.ucf (1536, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s250e_ft256_tr_a.ucf (1524, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s250e_pq208_tl_a.ucf (1394, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s250e_pq208_tr_a.ucf (1553, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s250e_vq100_t_a.ucf (1568, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s500e_cp132_t_a.ucf (1537, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s500e_fg320_tl_a.ucf (1219, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s500e_ft256_tl_a.ucf (1536, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s500e_ft256_tr_a.ucf (1524, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s500e_pq208_tl_a.ucf (1394, 2007-11-14)
xapp485\4bit_constraints\top4_rx_3s500e_pq208_tr_a.ucf (1553, 2007-11-14)
xapp485\4bit_floorplans (0, 2008-05-06)
xapp485\4bit_floorplans\top4_rx_3s100e_vq100_t_a.ppt (87552, 2006-05-01)
xapp485\4bit_floorplans\top4_rx_3s1200e_fg320_tl_a.ppt (89088, 2006-02-25)
xapp485\4bit_floorplans\top4_rx_3s1200e_fg320_tr_a.ppt (93184, 2006-02-25)
xapp485\4bit_floorplans\top4_rx_3s1200e_ft256_tl_a.ppt (90112, 2006-05-01)
xapp485\4bit_floorplans\top4_rx_3s1200e_ft256_tr_a.ppt (90112, 2006-05-01)
xapp485\4bit_floorplans\top4_rx_3s1600e_fg320_tl_a.ppt (88576, 2006-03-01)
xapp485\4bit_floorplans\top4_rx_3s1600e_fg320_tr_a.ppt (83968, 2006-03-01)
xapp485\4bit_floorplans\top4_rx_3s1600e_fg484_tl_a.ppt (81920, 2006-03-01)
xapp485\4bit_floorplans\top4_rx_3s250e_cp132_t_a.ppt (88064, 2006-05-01)
xapp485\4bit_floorplans\top4_rx_3s250e_ft256_tl_a.ppt (95232, 2006-05-01)
xapp485\4bit_floorplans\top4_rx_3s250e_ft256_tr_a.ppt (95232, 2006-05-01)
xapp485\4bit_floorplans\top4_rx_3s250e_vq100_t_a.ppt (90112, 2006-05-01)
xapp485\4bit_floorplans\top4_rx_3s500e_cp132_t_a.ppt (88576, 2006-05-01)
xapp485\4bit_floorplans\top4_rx_3s500e_fg320_tl_a.ppt (89600, 2006-03-21)
xapp485\4bit_floorplans\top4_rx_3s500e_ft256_tl_a.ppt (90624, 2006-05-01)
... ...

****************************************************************************** ** ** Xilinx, Inc. 2008 www.xilinx.com ** ** XAPP485 - 1:7 Data Deserialization in Spartan-3E/3A Devices at Speeds ** Up to 666 Mbps ** ******************************************************************************* ** ** Author : Xilinx, Inc. ** ** Disclaimer: ** LIMITED WARRANTY AND DISCLAIMER. These designs are ** provided to you "as is". Xilinx and its licensors make and you ** receive no warranties or conditions, express, implied, ** statutory or otherwise, and Xilinx specifically disclaims any ** implied warranties of merchantability, non-infringement, or ** fitness for a particular purpose. Xilinx does not warrant that ** the functions contained in these designs will meet your ** requirements, or that the operation of these designs will be ** uninterrupted or error free, or that defects in the Designs ** will be corrected. Furthermore, Xilinx does not warrant or ** make any representations regarding use or the results of the ** use of the designs in terms of correctness, accuracy, ** reliability, or otherwise. ** ** LIMITATION OF LIABILITY. In no event will Xilinx or its ** licensors be liable for any loss of data, lost profits, cost ** or procurement of substitute goods or services, or for any ** special, incidental, consequential, or indirect damages ** arising from the use or operation of the designs or ** accompanying documentation, however caused and on any theory ** of liability. This limitation will apply even if Xilinx ** has been advised of the possibility of such damage. This ** limitation shall apply not-withstanding the failure of the ** essential purpose of any limited remedies herein. ** ** Copyright (c) 2008 Xilinx, Inc. ** All rights reserved ** ******************************************************************************** Enclosed in these folders are the files needed to generate 1:7 deserialization designs as described in the application note XAPP485. Included are A. Source code in verilog and vhdl for both 4 and 5 bit receiver designs B. Recommended pinouts in the form of ucf files for various device/package combinations The format of the constraints file name is NAME_XX_Y.ucf - NAME is the name of the design XX is the position of the macro (for example : tl = top left, rb = right bottom) Y is a, b, c etc when there is more than one file C. Floorplan details in Microsoft PowerPoint format for the above D. A Microsoft Excel spreadsheet that enables the calculation of system margin and timespecs when bit rate information is inserted. Version 1.2 - May 2008 - Spreadsheet updated to tie up with new version of the app note Version 1.1.1 - November 2007 - Modified syntax of all rloc_origin statements in .ucf files - tested with release 9.2.03i of the Xilinx toolset Version 1.1 - November 2006 - Pin swapping logic as in XAPP491 added - (Optional) Auto phase alignment function added - Tested with release 8.2.03 of the Xilinx toolset Version 1.0 - March 2006 - initial release, tested with release 8.1.02 of the Xilinx toolset

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