说明：  针对嵌入式系统的底层网络接口给出了一种由FPGA实现的以太网控制器的设计方法．该控制器能支持10Mbps和100Mbps的传输速率以及半双工和全双工模式，同时可提供MII接口，可并通过外接以太网物理层（PHY）芯片来实现网络接入
(Embedded systems for the bottom of this paper, a network interface from FPGA to achieve the Ethernet controller design method. The controller will support the 10Mbps and 100Mbps transfer rate, as well as half-duplex and full-duplex mode, at the same time provides MII interface, and through external Ethernet physical layer (PHY) chip to achieve network access)