ISE
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:50137KB
下载次数:192
上传日期:2008-07-31 14:13:41
上 传 者:
xawl
说明: 学习Xilinx公司开发软件ISE的基础资料,从最基础到复杂逻辑设计。
(Learning Xilinx software ISE developed the basis of information from the most basic to complex logic design.)
文件列表:
ISE\demo1.swf (27491887, 2005-09-11)
ISE\Example-10-1\I2C\modelsim\0719.wlf (32768, 2004-07-19)
ISE\Example-10-1\I2C\modelsim\comp.wlf (32768, 2004-07-22)
ISE\Example-10-1\I2C\modelsim\format.do (2033, 2004-07-26)
ISE\Example-10-1\I2C\modelsim\I2C.cr.mti (2782, 2004-07-29)
ISE\Example-10-1\I2C\modelsim\I2C.mpf (18439, 2004-07-29)
ISE\Example-10-1\I2C\modelsim\I2C_mapped.cr.mti (1604, 2004-07-29)
ISE\Example-10-1\I2C\modelsim\I2C_mapped.mpf (16031, 2004-07-29)
ISE\Example-10-1\I2C\modelsim\rtl_ok.wlf (49152, 2004-07-22)
ISE\Example-10-1\I2C\modelsim\simprim\dcm_clock_divide_by_2\dcm_clock_divide_by_2_v.asm (5153, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\dcm_clock_divide_by_2\dcm_clock_divide_by_2_v.dat (771, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\dcm_clock_divide_by_2\_primary.dat (242, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\dcm_clock_lost\dcm_clock_lost_v.asm (7678, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\dcm_clock_lost\dcm_clock_lost_v.dat (1633, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\dcm_clock_lost\_primary.dat (179, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\dcm_maximum_period_check\dcm_maximum_period_check_v.asm (5585, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\dcm_maximum_period_check\dcm_maximum_period_check_v.dat (1019, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\dcm_maximum_period_check\_primary.dat (311, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\vcomponents\_primary.dat (371250, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\vcomponents\_vhdl.asm (8520, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\vpackage\body.asm (111456, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\vpackage\body.dat (17340, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\vpackage\_primary.dat (12470, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\vpackage\_vhdl.asm (16744, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and16\x_and16_v.asm (23684, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and16\x_and16_v.dat (2386, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and16\_primary.dat (2651, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and2\x_and2_v.asm (4656, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and2\x_and2_v.dat (764, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and2\_primary.dat (627, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and3\x_and3_v.asm (6010, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and3\x_and3_v.dat (882, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and3\_primary.dat (753, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and32\x_and32_v.asm (45563, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and32\x_and32_v.dat (4272, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and32\_primary.dat (4474, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and4\x_and4_v.asm (7364, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and4\x_and4_v.dat (992, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and4\_primary.dat (879, 2004-07-27)
ISE\Example-10-1\I2C\modelsim\simprim\x_and5\x_and5_v.asm (8718, 2004-07-27)
... ...
Revised: 1/31/00 MPG
Design Description: PN Generator Using the Virtex SRL Macro
For a full functional description see Application Note 211.
Design Type: ISE (chip V300 BG432 -6)
Source File:
pn_gen_srl_test.tf - Top-level, self-checking test bench that instantiates the pn generator. This verilog test bench works with both (Verilog and VHDL) versions of the design. ModelSim EE Plus/5.2e will support mixed HDL simulations.
iq_pn_gen.v - Verilog RTL version of pn generator code.
pni_gold.dat - "Golden" I channel data used by the test bench to compare against actual
pn sequence generated by the design.
pnq_gold.dat - "Golden" Q channel data used by the test bench to compare against actual
pn sequence generated by the design.
Synthesis:
Comments are provided in the verilog (iq_pn_gen.v) PN generator RTL code
that indicate what parameters are available to customize the implementation.
The number of taps are fixed however the tap points and LFSR width are
parameratizable.
All three synthesis vendors, Synplify 2.2.2a, FPGA Express 3.3, and Leonardo
v1999.1g were used to implement the LFSRs very efficiently utilizing the
Virtex Shift Register LUT (SRL16E).
The code provides a `define compiler directive that can be used to steer the code
to infer Flip-flops instead of SRL16E elements. This can be useful allowing the
code to be written such that it takes advantage of the Virtex SRL16Es when targetting
Virtex, but also allows for easy portability to other non-Virtex technologies.
Simulation:
Requires the following simulation libraries:
Unisims
Simprims
Using ModelSim, compile the pn_gen_srl_test.v and either the verilog version (iq_pn_gen.v)
or VHDL version (iq_pn_gen.vhd) of the pn generator. The clock period is set in the test
bench for 10ns. The example LFSRs in the code have a length of 17 bits wide therefore they
will produce a pn sequence 2^^17 - 1 bits long (before repeating). Run the simulation for
approximately 1.32 ms to simulate the entire sequence. (At a 10 ns clock period, the entire
sequence will take 1,310,710 ns.)
The test bench is self-checking and will compare the output of the I channel LFSR and Q channel
LFSR with "golden" data from the pni_gold.dat and pnq_gold.dat files, respectively. Each bit
comparison is reported in the command window showing the simulation time, the golden bit value,
and the actual bit value. If there's a mismatch between the two bits, the simluation will stop.
The test bench will also produce two files containing the actual bits generated. Bits generated
from the I channel LFSR will be written in a file called pni_testout.dat, and bits generated
from the Q channel LFSR will be written in a file called pnq_testout.dat.
NOTE: This design has been tested and is known to compile and implement
correctly using XST Synthesis flow.
Other synthesis flows are unsupported and may encounter errors in either
synthesis or implementation.
NOTE: If you are trying to run this example in a read-only location,
the design hierachy will not display properly. Please copy the example
project to a new location by using either Project Save As... from the File menu
pulldown in ISE or some other method of your choice. Copy the example to a location
where you have write permissions and the hiearchy will display properly.
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