clock
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：78KB
下载次数：5
上传日期：2008-08-02 21:26:52
上 传 者：
kenychen
说明： dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过.
(dp_xiliux the CPLD Verilog design experiments, clock demo. code test.)
文件列表:
clock (0, 2007-07-22)
clock\automake.log (14958, 2002-11-18)
clock\clock.bld (7961, 2002-11-18)
clock\clock.gyd (1066, 2002-11-18)
clock\clock.jed (102350, 2002-11-18)
clock\clock.jhd (14, 2002-11-18)
clock\clock.jid (46, 2002-11-18)
clock\clock.mfd (69771, 2002-11-18)
clock\clock.ngc (52282, 2002-11-18)
clock\clock.ngd (98193, 2002-11-18)
clock\clock.npl (209, 2002-11-18)
clock\clock.pnx (1078, 2002-11-18)
clock\clock.prj (100, 2002-11-18)
clock\clock.ptf (94, 2002-11-18)
clock\clock.rpt (57523, 2002-11-18)
clock\clock.syr (4731, 2002-11-18)
clock\clock.ucf (388, 2002-11-18)
clock\clock.v (2213, 2002-11-18)
clock\clock.vm6 (365821, 2002-11-18)
clock\clock.xst (412, 2002-11-18)
clock\clock_ngdbuild.nav (53, 2002-11-18)
clock\clock._prj (112, 2002-11-18)
clock\last_used.ucf (388, 2002-11-18)
clock\ngdbuild.rsp (59, 2002-11-18)
clock\tmperr.err (0, 2002-11-18)
clock\_chipview.tcl (1293, 2002-11-18)
clock\_cpldfit.rsp (124, 2002-11-18)
clock\_cpldfit.tcl (691, 2002-11-18)
clock\_impact.log (1171, 2002-11-18)
clock\_ngdbld.rsp (3, 2002-11-18)
clock\__clock_2prj_exewrap.rsp (111, 2002-11-18)
clock\__impact.rsp (57, 2002-11-18)
clock\__projnav.log (14909, 2002-11-18)
clock\_ngo (0, 2007-07-22)
clock\_ngo\netlist.lst (47, 2002-11-18)
近期下载者：
相关文件：
收藏者：