DE2_TV

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:137KB
下载次数:13
上传日期:2008-08-06 21:13:56
上 传 者lingyunzhihuaxu
说明:  用于Altera公司DE2开发板的TV demonstration
(Altera Corporation for DE2 development board of the TV demonstration)

文件列表:
DE2_TV\AUDIO_DAC.v (8754, 2005-08-15)
DE2_TV\DE2_TV.pof (2097354, 2006-11-20)
DE2_TV\DE2_TV.qpf (944, 2005-10-05)
DE2_TV\DE2_TV.qsf (26171, 2006-11-20)
DE2_TV\DE2_TV.sof (841105, 2006-11-20)
DE2_TV\DE2_TV.v (19730, 2006-11-20)
DE2_TV\DIV.v (4346, 2006-08-10)
DE2_TV\I2C_AV_Config.v (4840, 2006-08-04)
DE2_TV\I2C_Controller.v (3885, 2005-08-30)
DE2_TV\ITU_656_Decoder.v (2813, 2006-08-16)
DE2_TV\Line_Buffer.v (4037, 2006-08-16)
DE2_TV\MAC_3.v (14506, 2006-08-11)
DE2_TV\PLL.v (13818, 2006-08-13)
DE2_TV\Reset_Delay.v (497, 2006-01-06)
DE2_TV\Sdram_Control_4Port\command.v (17066, 2005-08-23)
DE2_TV\Sdram_Control_4Port\control_interface.v (5812, 2005-08-23)
DE2_TV\Sdram_Control_4Port\Sdram_Control_4Port.v (15676, 2006-10-26)
DE2_TV\Sdram_Control_4Port\Sdram_Params.h (1542, 2006-08-09)
DE2_TV\Sdram_Control_4Port\Sdram_PLL.ppf (416, 2006-11-20)
DE2_TV\Sdram_Control_4Port\Sdram_PLL.v (16581, 2006-11-20)
DE2_TV\Sdram_Control_4Port\Sdram_RD_FIFO.v (7847, 2006-08-09)
DE2_TV\Sdram_Control_4Port\Sdram_WR_FIFO.v (7847, 2006-08-09)
DE2_TV\Sdram_Control_4Port\sdr_data_path.v (909, 2005-08-26)
DE2_TV\SEG7_LUT.v (705, 2005-09-17)
DE2_TV\SEG7_LUT_8.v (458, 2005-08-25)
DE2_TV\TD_Detect.v (647, 2006-08-16)
DE2_TV\TP_RAM.v (7885, 2006-08-24)
DE2_TV\VGA_Ctrl.v (2818, 2006-08-24)
DE2_TV\YCbCr2RGB.v (3403, 2006-08-12)
DE2_TV\YUV422_to_444.v (734, 2006-08-13)
DE2_TV\Sdram_Control_4Port (0, 2008-08-06)
DE2_TV (0, 2008-08-06)

DE2_Tv ------ This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically; press KEY0 to force the design to resynchronize. Running the Design ------------------ 1) Launch the Quartus II software. 2) Open the DE2_Tv.qpf project located in the \DE2_Tv folder. (File menu -> Open Project) 3) Open the Programmer window. (Tools menu -> Programmer) 4) The DE2_Tv.sof programming file should be listed. Check the 'Program/Configure' box and set up the JTAG programming hardware connection via the 'Hardware Setup' button. 5) Press 'Start' to start programming. The design should now be programmed and running. User Inputs to the Design ------------------------- KEY0: resets the circuit and resynchronizes with the input video Compiling the Design -------------------- 1) Launch the Quartus II software. 2) Open the DE2_Tv.qpf project located in the \DE2_Tv folder. (File menu -> Open Project) 3) Start compilation. (Processing -> Start Compilation) 4) After compilation is finished, you can run the design with the generated SOF file. See 'Running the Design' above.

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