gate
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：166KB
下载次数：7
上传日期：2008-08-17 15:42:28
上 传 者：
honly
说明： verilog中调用门级电路的实验程序，实现了门级舰模
(call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode)
文件列表:
gate\gate.qpf (941, 2008-08-04)
gate\gate.qsf (2941, 2008-08-08)
gate\db\gate.db_info (136, 2008-08-04)
gate\db\gate.cmp.rdb (10373, 2008-08-08)
gate\db\gate.tan.qmsg (1282, 2008-08-08)
gate\db\gate.sld_design_entry.sci (135, 2008-08-08)
gate\db\gate.pre_map.cdb (505, 2008-08-08)
gate\db\gate.rtlv.hdb (5371, 2008-08-08)
gate\db\gate.map.qmsg (3725, 2008-08-08)
gate\db\gate.(0).cnf.cdb (442, 2008-08-08)
gate\db\gate.eco.cdb (141, 2008-08-08)
gate\db\gate_cmp.qrpt (0, 2008-08-04)
gate\db\gate.cbx.xml (86, 2008-08-08)
gate\db\gate.hif (418, 2008-08-08)
gate\db\gate.map.hdb (5187, 2008-08-08)
gate\db\gate.rtlv_sg_swap.cdb (158, 2008-08-08)
gate\db\gate.fit.qmsg (12561, 2008-08-08)
gate\db\gate.(0).cnf.hdb (682, 2008-08-08)
gate\db\gate.eda.qmsg (1415, 2008-08-08)
gate\db\gate.pre_map.hdb (5372, 2008-08-08)
gate\db\gate.sgdiff.cdb (468, 2008-08-08)
gate\db\gate.sim.qmsg (1329, 2008-08-05)
gate\db\gate.sim.vwf (3410, 2008-08-05)
gate\db\gate.sim.rdb (1493, 2008-08-05)
gate\db\gate.map.cdb (569, 2008-08-08)
gate\db\gate.sim.hdb (2615, 2008-08-05)
gate\db\gate.asm.qmsg (1106, 2008-08-08)
gate\db\gate.rtlv_sg.cdb (471, 2008-08-08)
gate\db\gate.sgdiff.hdb (5369, 2008-08-08)
gate\db\gate.sld_design_entry_dsc.sci (135, 2008-08-08)
gate\db\gate.hier_info (101, 2008-08-08)
gate\db\gate.eds_overflow (2, 2008-08-05)
gate\db\gate_sim.qrpt (0, 2008-08-04)
gate\db\gate.cmp0.ddb (12978, 2008-08-08)
gate\db\gate.cmp.cdb (923, 2008-08-08)
gate\db\gate.signalprobe.cdb (374, 2008-08-08)
gate\db\gate.psp (0, 2008-08-08)
gate\db\gate.cmp.hdb (5246, 2008-08-08)
gate\db\gate.cmp.tdb (352, 2008-08-08)
gate\db\gate.syn_hier_info (0, 2008-08-08)
... ...
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