an499_design_example
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：423KB
下载次数：142
上传日期：2008-09-04 10:45:09
上 传 者：
wangkj
说明： cpld 控制 8-32M sdram 控制器 maxII epm570实现。
(CPLD control 8-32M sdram controller maxII epm570 realize.)
文件列表:
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code\addr_gen.v (1140, 2007-03-24)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code\mobile_sdram.v (8796, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code\upcount_2.v (768, 2007-03-24)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code\upcount_4.v (766, 2007-03-24)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\code (0, 2008-08-04)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\addr_gen.v (1140, 2007-03-24)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\mobile_sdram.cr.mti (1809, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\mobile_sdram.mpf (11356, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\mobile_sdram.v (8796, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\test_mob_sdram.v (4599, 2007-03-29)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\upcount_2.v (768, 2007-03-24)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\upcount_4.v (766, 2007-03-24)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\vsim.wlf (40960, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.bmp (452034, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.do (1629, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\addr_gen\verilog.psm (9199, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\addr_gen\_primary.dat (897, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\addr_gen\_primary.vhd (647, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\addr_gen (0, 2008-06-16)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\mobile_sdram\verilog.psm (61492, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\mobile_sdram\_primary.dat (6125, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\mobile_sdram\_primary.vhd (2055, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\mobile_sdram (0, 2008-06-16)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_mob_sdram\verilog.psm (23102, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_mob_sdram\_primary.dat (2855, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_mob_sdram\_primary.vhd (88, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_mob_sdram (0, 2008-06-16)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_2\verilog.psm (3442, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_2\_primary.dat (326, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_2\_primary.vhd (285, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_2 (0, 2008-06-16)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_4\verilog.psm (3442, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_4\_primary.dat (338, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_4\_primary.vhd (285, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\upcount_4 (0, 2008-06-16)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work\_info (1824, 2007-03-27)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim\work (0, 2008-06-16)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\modelsim (0, 2008-06-16)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\addr_gen.v (1140, 2007-03-24)
an499_design_example\Mobile_DRAM_Altera_MAX_II_CPLD_Design_Example\quartus\db\mobile_sdram.(0).cnf.cdb (13660, 2008-06-16)
... ...
近期下载者：
相关文件：
收藏者：