xapp208
所属分类:图形图象
开发工具:VHDL
文件大小:8KB
下载次数:49
上传日期:2008-09-05 18:59:20
上 传 者:
chxleefd
说明: xilinx 基于查找表方法实现的IDCT的verilog源码
(Xilinx LUT-based method to achieve the IDCT of the Verilog source code)
文件列表:
big_lut.v (11493, 1999-08-31)
byte_mult.v (7739, 1999-08-31)
idct.v (10108, 1999-08-31)
testbench.v (3787, 1999-08-31)
Date: Wed. Jun 9, 1999
File Name:
Description:
Contains the following files
readme.txt big_lut.v byte_mult.v idct.v testbench.v
Platform:
All
Synthesis Tools:
Use Synplicity or Leonardo (Exemplar).
Known Issues:
Will not compile with FPGA Express.
Installation/Use:
Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
Who to Contact if you have problems?
kamal.chaudhary@xilinx.com
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