文件列表:

sjall\SJ\FPGA\device_usage_statistics.html (25524, 2008-07-07)
sjall\SJ\FPGA\DLL.cmd_log (4779, 2008-07-08)
sjall\SJ\FPGA\DLL.jhd (12, 2008-07-07)
sjall\SJ\FPGA\DLL.sch (4152, 2008-07-07)
sjall\SJ\FPGA\DLL.schbak (4152, 2008-07-07)
sjall\SJ\FPGA\DLL.schcmd (88, 2008-07-07)
sjall\SJ\FPGA\DLL.schlog (0, 2008-07-10)
sjall\SJ\FPGA\DLL.sym (495, 2008-07-07)
sjall\SJ\FPGA\DLL.vhf (3581, 2008-07-08)
sjall\SJ\FPGA\FIFO.asy (873, 2008-07-07)
sjall\SJ\FPGA\FIFO.ngc (131518, 2008-07-07)
sjall\SJ\FPGA\FIFO.sym (1475, 2008-07-07)
sjall\SJ\FPGA\FIFO.v (5206, 2008-07-07)
sjall\SJ\FPGA\FIFO.veo (3089, 2008-07-07)
sjall\SJ\FPGA\FIFO.vhd (5418, 2008-07-07)
sjall\SJ\FPGA\FIFO.vho (3653, 2008-07-07)
sjall\SJ\FPGA\FIFO.xco (2215, 2008-07-07)
sjall\SJ\FPGA\FIFO_fifo_generator_v3_2_xst_1.lso (63, 2008-07-07)
sjall\SJ\FPGA\FIFO_fifo_generator_v3_2_xst_1_vhdl.prj (14057, 2008-07-07)
sjall\SJ\FPGA\FIFO_flist.txt (185, 2008-07-07)
sjall\SJ\FPGA\fifo_generator_release_notes.txt (4581, 2008-07-07)
sjall\SJ\FPGA\fifo_generator_ug175.pdf (892639, 2008-07-07)
sjall\SJ\FPGA\FIFO_xmdf.tcl (3144, 2008-07-07)
sjall\SJ\FPGA\FPGA.ise (414340, 2008-07-10)
sjall\SJ\FPGA\FPGA.ise_ISE_Backup (414208, 2008-07-10)
sjall\SJ\FPGA\FPGA.ntrc_log (817, 2008-07-10)
sjall\SJ\FPGA\pepExtractor.prj (39, 2008-07-10)
sjall\SJ\FPGA\reportgen.log (2888, 2008-07-08)
sjall\SJ\FPGA\sjall.bgn (5282, 2008-07-10)
sjall\SJ\FPGA\sjall.bit (78827, 2008-07-10)
sjall\SJ\FPGA\sjall.bld (6238, 2008-07-10)
sjall\SJ\FPGA\sjall.cel (0, 2008-07-08)
sjall\SJ\FPGA\sjall.clk_rgn (223, 2008-07-08)
sjall\SJ\FPGA\sjall.cmd_log (29324, 2008-07-10)
sjall\SJ\FPGA\sjall.dly (84614, 2008-07-08)
sjall\SJ\FPGA\sjall.drc (244, 2008-07-10)
sjall\SJ\FPGA\sjall.ibs (74596, 2008-07-08)
sjall\SJ\FPGA\sjall.jhd (119, 2008-07-10)
sjall\SJ\FPGA\sjall.lck (1533, 2008-07-08)
... ...

The following files were generated for 'FIFO' in directory E:\Application\SJ\FPGA: FIFO.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. FIFO.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. FIFO.sym: Please see the core data sheet. FIFO.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. FIFO.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. FIFO.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. FIFO.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. FIFO.xco: CORE Generator input file containing the parameters used to regenerate a core. FIFO_fifo_generator_v3_2_xst_1_vhdl.prj: Please see the core data sheet. FIFO_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. FIFO_readme.txt: Text file indicating the files generated and how they are used. FIFO_xmdf.tcl: Please see the core data sheet. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：