wb_rtc
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：8KB
下载次数：27
上传日期：2008-09-08 10:43:57
上 传 者：
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说明： // -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined
(//-*- Mode: Verilog-*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined)
文件列表:
wb_rtc (0, 2003-08-02)
wb_rtc\bench (0, 2003-08-02)
wb_rtc\bench\Verilog (0, 2003-08-02)
wb_rtc\bench\Verilog\clkrst.v (906, 2003-08-02)
wb_rtc\bench\Verilog\tb_top.v (4317, 2003-08-02)
wb_rtc\bench\Verilog\timescale.v (20, 2001-08-22)
wb_rtc\bench\Verilog\wb_master.v (4669, 2002-12-27)
wb_rtc\rtl (0, 2003-08-02)
wb_rtc\rtl\Verilog (0, 2003-08-02)
wb_rtc\rtl\Verilog\wb_rtc.v (22504, 2003-08-02)
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