mult

所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:59KB
下载次数:68
上传日期:2008-09-10 22:35:03
上 传 者zhangc03
说明:  64位乘法器源码verilog,经过验证测试
(64-bit multiplier source verilog, validated test)

文件列表:
addsub.v (561, 2005-04-05)
addsub2.v (523, 2005-04-05)
addsub3.v (554, 2005-04-05)
addsub_c_11.v (310, 2005-04-06)
addsub_c_13.v (330, 2005-04-06)
addsub_c_15.v (348, 2005-04-06)
addsub_c_9.v (248, 2005-04-06)
array_mult.v (1194, 2005-03-03)
array_mult_map.v (15072, 2005-02-04)
array_mult_tb.v (1473, 2005-04-08)
array_mult_timesim.v (49047, 2005-04-08)
array_mult_translate.v (35449, 2005-02-07)
boothcode.v (859, 2005-04-05)
booth_mult.v (1113, 2005-04-06)
booth_mult_tb.v (1498, 2005-04-06)
booth_mult_timesim.v (57965, 2005-04-06)
bw_mult.v (493, 2005-04-07)
bw_mult_tb.v (1484, 2005-04-07)
bw_mult_timesim.v (67582, 2005-04-07)
csa.v (204, 2005-04-08)
fulladd.v (218, 2005-02-04)
lastrow.v (588, 2005-02-04)
mult.v (117, 2005-02-04)
multcell.v (428, 2005-02-04)
multrow.v (647, 2005-02-04)
mult_1.v (174, 2005-04-08)
mult_const.v (1201, 2005-02-04)
mult_const2.v (146, 2005-02-07)
mult_s.v (131, 2005-04-07)
mult_s_tb.v (1478, 2005-04-07)
mult_s_timesim.v (69953, 2005-04-07)
wallace.v (1097, 2005-04-08)
wallace_tb.v (1455, 2005-04-08)
wallace_timesim.v (60350, 2005-04-08)
y_mux.v (306, 2005-04-06)

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