AlteraSdramIP
所属分类：VHDL/FPGA/Verilog
开发工具：MultiPlatform
文件大小：763KB
下载次数：44
上传日期：2008-09-15 09:45:43
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说明： Altera Sdram IP 源码，VHDL写的
(Altera Sdram IP source code, VHDL written)
文件列表:
CVS (0, 2002-09-02)
doc (0, 2002-09-02)
doc\CVS (0, 2002-09-02)
license.txt (12583, 2004-08-25)
sdr_sdram.pdf (917283, 2002-09-02)
simulation (0, 2002-09-02)
simulation\CVS (0, 2002-09-02)
simulation\sdr_sdram_tb.vhd (29794, 2002-09-02)
source (0, 2002-09-02)
source\Command.vhd (16762, 2002-09-02)
source\control_interface.vhd (9345, 2002-09-02)
source\CVS (0, 2002-09-02)
source\pll1.vhd (4718, 2000-06-06)
source\sdr_data_path.vhd (2595, 2002-09-02)
source\sdr_sdram.vhd (15447, 2002-09-02)
SDR SDRAM Controller v1.1 readme.txt
This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture.
Last updated September, 2002
Copyright 2002 Altera Corporation. All rights reserved.
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