multiply

所属分类:数学计算
开发工具:VHDL
文件大小:4KB
下载次数:205
上传日期:2008-09-22 11:27:30
上 传 者xinxin_1200
说明:  这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.
(This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.)

文件列表:
download multiply\bootcoder.v (472, 2008-01-28)
download multiply\boot_mul.v (8627, 2008-07-17)
download multiply\csa.v (211, 2008-01-28)
download multiply\tb_bootmul.v (619, 2008-01-28)
download multiply\tb_mul.v (663, 2008-01-28)
download multiply\_42c_l.v (463, 2008-07-17)
download multiply (0, 2008-07-17)

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