viterbi
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：222KB
下载次数：158
上传日期：2008-09-25 20:55:21
上 传 者：
dhjie1981
说明： 一个完整的viterbi编码程序，使用vhdl语言编写，还有测试程序
(A complete viterbi coding procedures, the use of VHDL language, as well as test procedures)
文件列表:
Quartus_II\run_script.tcl (5704, 2004-10-14)
Quartus_II\viterbi_node_sync.qpf (1571, 2004-10-14)
Quartus_II\viterbi_node_sync.qsf (6710, 2004-10-14)
Quartus_II\wave.do (2729, 2004-10-14)
source\a_rcvsym.txt (126978, 2004-10-14)
source\a_txsym.txt (126976, 2004-10-14)
source\ber_node_sync.vhd (3334, 2004-10-05)
source\BER_report.txt (2924, 2004-10-14)
source\ber_threshold.vhd (4294, 2004-10-05)
source\block_period_stim.txt (208, 2004-10-14)
source\mux_2d.vhd (6016, 2004-09-13)
source\rotate_node_sync.vhd (2756, 2004-10-05)
source\tcm_rcv_sector.txt (0, 2004-10-14)
source\transbit.txt (86016, 2004-10-14)
source\viterbi_BER.bsf (6342, 2004-10-14)
source\viterbi_BER.cmp (2540, 2004-10-14)
source\viterbi_BER.html (5844, 2004-10-14)
source\viterbi_BER.inc (2053, 2004-10-14)
source\viterbi_BER.vhd (16979, 2004-10-14)
source\viterbi_BER.vho (1436657, 2004-10-14)
source\viterbi_BER_bb.v (2497, 2004-10-14)
source\viterbi_BER_inst.vhd (2462, 2004-10-14)
source\viterbi_BER_logiclock_script.tcl (2669, 2004-10-14)
source\viterbi_BER_testbench.vhd (9836, 2004-10-14)
source\viterbi_BER_vital_script.tcl (2208, 2004-10-14)
source\viterbi_BER_vsim_script.tcl (3973, 2004-10-14)
source\viterbi_node_sync.vhd (5481, 2004-10-14)
testbench\auk_vit_vit_var_enc_arc_rtl.vhd (1962, 2004-06-23)
testbench\auk_vit_vit_var_enc_ent.vhd (1076, 2004-06-23)
testbench\Bench_vit_par_atl_arc_ben_node_sync.vhd (26850, 2004-10-05)
testbench\Bench_vit_par_atl_ent_node_sync.vhd (3462, 2004-10-14)
testbench\viterbi_node_sync_testbench.vhd (10804, 2004-10-14)
testbench\vi_bench.vhd (14902, 2004-06-23)
testbench\vi_functions.vhd (38860, 2004-06-23)
testbench\vi_interface.vhd (12324, 2004-06-23)
Quartus_II (0, 2004-10-14)
source (0, 2004-10-14)
testbench (0, 2004-10-14)
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