ref-sdr-sdram-verilog
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：701KB
下载次数：228
上传日期：2008-09-29 20:23:35
上 传 者：
ilove314
说明： SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块
(SDRAM)
文件列表:
ref-sdr-sdram-verilog\sdr_sdram.pdf (917283, 2002-09-02)
ref-sdr-sdram-verilog\simulation\sdr_sdram_tb.v (22444, 2000-07-12)
ref-sdr-sdram-verilog\source\altclklock.v (8543, 2000-06-12)
ref-sdr-sdram-verilog\source\Command.v (17328, 2000-07-28)
ref-sdr-sdram-verilog\source\compile_all.v (206, 2000-05-19)
ref-sdr-sdram-verilog\source\control_interface.v (8463, 2000-07-28)
ref-sdr-sdram-verilog\source\Params.v (935, 2000-07-06)
ref-sdr-sdram-verilog\source\PLL1.v (4754, 2000-05-23)
ref-sdr-sdram-verilog\source\sdr_data_path.v (2747, 2000-07-28)
ref-sdr-sdram-verilog\source\sdr_sdram.v (6942, 2000-07-28)
ref-sdr-sdram-verilog\doc (0, 2002-09-11)
ref-sdr-sdram-verilog\simulation (0, 2002-09-11)
ref-sdr-sdram-verilog\source (0, 2002-09-11)
ref-sdr-sdram-verilog (0, 2008-09-01)
SDR SDRAM Controller v1.1 readme.txt
This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture.
Last updated September, 2002
Copyright 2002 Altera Corporation. All rights reserved.
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