dds
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：547KB
下载次数：920
上传日期：2008-10-01 18:09:25
上 传 者：
chen2017chen
说明： 基于VHDL+FPGA的DDS信号发生设计，已经通过调式
(Based on VHDL+ FPGA design of the DDS signal has been through mode)
文件列表:
dds\dds.qpf (908, 2008-09-30)
dds\dds.qsf (1909, 2008-10-01)
dds\db\wed.wsf (12619, 2008-10-01)
dds\db\dds.db_info (137, 2008-09-30)
dds\db\dds.map.qmsg (7660, 2008-10-01)
dds\db\dds.sld_design_entry.sci (154, 2008-10-01)
dds\db\dds.cmp.rdb (24659, 2008-10-01)
dds\db\dds.analyze_file.qmsg (1758, 2008-10-01)
dds\db\dds.map_bb.logdb (4, 2008-10-01)
dds\db\dds.fit.qmsg (37147, 2008-10-01)
dds\db\dds.rtlv.hdb (13189, 2008-10-01)
dds\db\dds.eco.cdb (161, 2008-10-01)
dds\db\dds.cbx.xml (202, 2008-10-01)
dds\db\prev_cmp_dds.map.qmsg (8164, 2008-10-01)
dds\db\dds.pre_map.hdb (13203, 2008-10-01)
dds\db\dds.pre_map.cdb (8365, 2008-10-01)
dds\db\dds.map.logdb (4, 2008-10-01)
dds\db\dds.(0).cnf.cdb (1632, 2008-10-01)
dds\db\dds.map.cdb (7713, 2008-10-01)
dds\db\dds.asm.qmsg (1821, 2008-10-01)
dds\db\dds.cmp0.ddb (33974, 2008-10-01)
dds\db\dds.(0).cnf.hdb (682, 2008-10-01)
dds\db\dds.(1).cnf.cdb (2581, 2008-10-01)
dds\db\dds.tan.qmsg (35481, 2008-10-01)
dds\db\dds.(1).cnf.hdb (973, 2008-10-01)
dds\db\dds.(2).cnf.cdb (1410, 2008-10-01)
dds\db\dds.cmp.logdb (4, 2008-10-01)
dds\db\dds.sgdiff.cdb (7057, 2008-10-01)
dds\db\dds.sgdiff.hdb (13693, 2008-10-01)
dds\db\prev_cmp_dds.sim.qmsg (3119, 2008-10-01)
dds\db\dds.(2).cnf.hdb (634, 2008-10-01)
dds\db\dds.cmp.ecobp (28, 2008-10-01)
dds\db\altsyncram_7q41.tdf (13838, 2008-09-30)
dds\db\dds.cmp_bb.logdb (4, 2008-10-01)
dds\db\prev_cmp_dds.fit.qmsg (33572, 2008-10-01)
dds\db\dds.map.hdb (10066, 2008-10-01)
dds\db\altsyncram_n341.tdf (13991, 2008-09-30)
dds\db\dds.map.bpm (606, 2008-10-01)
dds\db\prev_cmp_dds.asm.qmsg (1821, 2008-10-01)
dds\db\altsyncram_rd31.tdf (2173, 2008-10-01)
... ...
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