verilog_risc
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：126KB
下载次数：155
上传日期：2008-10-18 17:56:07
上 传 者：
linqi
说明： RISC状态机由三个功能单元构成：处理器、控制器和存储器。
RISC状态机经优化可实现高效的流水线操作。
RISC 中的数据线为16位。
在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前
对这16个数进行排序，从大到小放置在18到33的位置
求出前16个数的平均数，放在34的位置
基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。
因为采用16位指令，有扩充的余地。
(RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.)
文件列表:
verilog实现简单risc\Address_Register.v (343, 2008-07-15)
verilog实现简单risc\Address_Register.v.bak (342, 2008-04-14)
verilog实现简单risc\Alu_RISC.v (833, 2008-07-15)
verilog实现简单risc\Alu_RISC.v.bak (822, 2008-07-15)
verilog实现简单risc\Clock_Unit .v (183, 2008-04-14)
verilog实现简单risc\Control_Unit.v (5072, 2008-07-16)
verilog实现简单risc\Control_Unit.v.bak (5046, 2008-07-16)
verilog实现简单risc\D_flop.v (269, 2008-04-14)
verilog实现简单risc\Instruction_Register.v (452, 2008-07-16)
verilog实现简单risc\Instruction_Register.v.bak (452, 2008-07-16)
verilog实现简单risc\Memory_Unit.v (409, 2008-07-15)
verilog实现简单risc\Memory_Unit.v.bak (408, 2008-04-14)
verilog实现简单risc\Multiplexer_3ch.v (304, 2008-07-15)
verilog实现简单risc\Multiplexer_3ch.v.bak (303, 2008-04-14)
verilog实现简单risc\Multiplexer_5ch.v (500, 2008-07-16)
verilog实现简单risc\Multiplexer_5ch.v.bak (413, 2008-07-15)
verilog实现简单risc\Processing_Unit.v (1907, 2008-07-16)
verilog实现简单risc\Processing_Unit.v.bak (1845, 2008-07-15)
verilog实现简单risc\Program_Counter.v (468, 2008-07-15)
verilog实现简单risc\Program_Counter.v.bak (467, 2008-07-15)
verilog实现简单risc\Register_Unit.v (353, 2008-07-15)
verilog实现简单risc\Register_Unit.v.bak (352, 2008-04-14)
verilog实现简单risc\risc.cr.mti (3963, 2008-07-16)
verilog实现简单risc\risc.mpf (51966, 2008-07-16)
verilog实现简单risc\risc1.cr.mti (3963, 2008-07-16)
verilog实现简单risc\risc1.mpf (51964, 2008-07-16)
verilog实现简单risc\RSIC_SPM.v (982, 2008-07-15)
verilog实现简单risc\RSIC_SPM.v.bak (981, 2008-07-15)
verilog实现简单risc\test_RISC_SPM.v (3178, 2008-07-15)
verilog实现简单risc\test_RISC_SPM.v.bak (3130, 2008-07-15)
verilog实现简单risc\transcript (4856, 2008-07-16)
verilog实现简单risc\vsim.wlf (32768, 2008-07-16)
verilog实现简单risc\work\@address_@register\verilog.asm (5868, 2008-07-16)
verilog实现简单risc\work\@address_@register\_primary.dat (354, 2008-07-16)
verilog实现简单risc\work\@address_@register\_primary.dbs (743, 2008-07-16)
verilog实现简单risc\work\@address_@register\_primary.vhd (397, 2008-07-16)
verilog实现简单risc\work\@alu_@r@i@s@c\verilog.asm (12479, 2008-07-16)
verilog实现简单risc\work\@alu_@r@i@s@c\_primary.dat (824, 2008-07-16)
verilog实现简单risc\work\@alu_@r@i@s@c\_primary.dbs (1489, 2008-07-16)
verilog实现简单risc\work\@alu_@r@i@s@c\_primary.vhd (796, 2008-07-16)
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