usb20_ipcore_usb_funct
所属分类：USB编程
开发工具：VHDL
文件大小：204KB
下载次数：155
上传日期：2008-10-20 17:35:23
上 传 者：
沙河骑士
说明： usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.
(usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.)
文件列表:
rtl\usbf_crc5.v (4875, 2003-10-17)
rtl\usbf_crc16.v (5521, 2003-10-17)
rtl\usbf_defines.v (11701, 2003-10-17)
rtl\usbf_ep_rf.v (14748, 2003-10-17)
rtl\usbf_ep_rf_dummy.v (6183, 2003-10-17)
rtl\usbf_mem_arb.v (6613, 2003-10-17)
rtl\usbf_rf.v (54058, 2003-10-17)
rtl\usbf_top.v (19114, 2003-11-11)
rtl\usbf_utmi_if.v (8247, 2003-11-11)
rtl\usbf_utmi_ls.v (18700, 2003-11-11)
rtl\usbf_wb.v (8271, 2003-10-17)
rtl\usbf_idma.v (18741, 2003-10-17)
rtl\usbf_pa.v (11136, 2003-10-17)
rtl\usbf_pd.v (13662, 2003-10-17)
rtl\usbf_pe.v (34487, 2003-10-17)
rtl\usbf_pl.v (15166, 2003-10-17)
rtl (0, 2006-09-21)
syn\bin\comp.dc (4267, 2001-08-03)
syn\bin\design_spec.dc (767, 2001-08-03)
syn\bin\lib_spec.dc (1156, 2001-08-03)
syn\bin\read.dc (1945, 2001-08-03)
syn\bin (0, 2006-09-21)
syn (0, 2006-09-21)
doc\STATUS.txt (1617, 2001-08-03)
doc\usb_doc.pdf (332432, 2002-01-27)
doc (0, 2006-09-21)
The USB 2.0 Function Project Page is:
http://www.opencores.org/cores/usb/
To find out more about me (Rudolf Usselmann), please visit:
http://www.asics.ws
Directory Structure
-------------------
[core_root]
|
+-doc Documentation
|
+-bench--+ Test Bench
| +- verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-rtl----+ Core RTL Sources
| +-verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-sim----+
| +-rtl_sim---+ Functional verification Directory
| | +-bin Makefiles/Run Scripts
| | +-run Working Directory
| |
| +-gate_sim--+ Functional & Timing Gate Level
| | Verification Directory
| +-bin Makefiles/Run Scripts
| +-run Working Directory
|
+-lint--+ Lint Directory Tree
| +-bin Makefiles/Run Scripts
| +-run Working Directory
| +-log Linter log & result files
|
+-syn---+ Synthesis Directory Tree
| +-bin Synthesis Scripts
| +-run Working Directory
| +-log Synthesis log files
| +-out Synthesis Output
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