usb_funct
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：192KB
下载次数：33
上传日期：2008-10-23 13:08:47
上 传 者：
dushibiao
说明： VHDL USB2.0接口源码,内有说明,详细.
(VHDL USB2.0 interface source code, which is described in detail.)
文件列表:
usb_funct\syn\run\CVS\Entries (2, 2001-08-19)
usb_funct\syn\run\CVS\Repository (18, 2001-08-19)
usb_funct\syn\run\CVS\Root (13, 2001-08-19)
usb_funct\syn\out\CVS\Entries (2, 2001-08-19)
usb_funct\syn\out\CVS\Repository (18, 2001-08-19)
usb_funct\syn\out\CVS\Root (13, 2001-08-19)
usb_funct\syn\log\CVS\Entries (2, 2001-08-19)
usb_funct\syn\log\CVS\Repository (18, 2001-08-19)
usb_funct\syn\log\CVS\Root (13, 2001-08-19)
usb_funct\syn\CVS\Entries (40, 2001-08-19)
usb_funct\syn\CVS\Repository (14, 2001-08-19)
usb_funct\syn\CVS\Root (13, 2001-08-19)
usb_funct\syn\bin\comp.dc (4138, 2001-08-03)
usb_funct\syn\bin\design_spec.dc (741, 2001-08-03)
usb_funct\syn\bin\lib_spec.dc (1120, 2001-08-03)
usb_funct\syn\bin\read.dc (1879, 2001-08-03)
usb_funct\syn\bin\CVS\Entries (173, 2001-08-19)
usb_funct\syn\bin\CVS\Repository (18, 2001-08-19)
usb_funct\syn\bin\CVS\Root (13, 2001-08-19)
usb_funct\sim\rtl_sim\run\CVS\Entries (2, 2001-08-19)
usb_funct\sim\rtl_sim\run\CVS\Repository (26, 2001-08-19)
usb_funct\sim\rtl_sim\run\CVS\Root (13, 2001-08-19)
usb_funct\sim\rtl_sim\CVS\Entries (20, 2001-08-19)
usb_funct\sim\rtl_sim\CVS\Repository (22, 2001-08-19)
usb_funct\sim\rtl_sim\CVS\Root (13, 2001-08-19)
usb_funct\sim\rtl_sim\bin\CVS\Entries (2, 2001-08-19)
usb_funct\sim\rtl_sim\bin\CVS\Repository (26, 2001-08-19)
usb_funct\sim\rtl_sim\bin\CVS\Root (13, 2001-08-19)
usb_funct\sim\CVS\Entries (14, 2001-08-19)
usb_funct\sim\CVS\Repository (14, 2001-08-19)
usb_funct\sim\CVS\Root (13, 2001-08-19)
usb_funct\rtl\verilog\usbf_crc16.v (4796, 2001-08-03)
usb_funct\rtl\verilog\usbf_crc5.v (4159, 2001-08-03)
usb_funct\rtl\verilog\usbf_defines.v (9328, 2001-08-10)
usb_funct\rtl\verilog\usbf_ep_rf.v (12004, 2001-08-03)
usb_funct\rtl\verilog\usbf_ep_rf_dummy.v (5399, 2001-08-03)
usb_funct\rtl\verilog\usbf_idma.v (12769, 2001-08-03)
usb_funct\rtl\verilog\usbf_mem_arb.v (5600, 2001-08-03)
usb_funct\rtl\verilog\usbf_pa.v (8620, 2001-08-10)
usb_funct\rtl\verilog\usbf_pd.v (12023, 2001-08-10)
... ...
The USB 2.0 Function Project Page is:
http://www.opencores.org/cores/usb/
To find out more about me (Rudolf Usselmann), please visit:
http://www.asics.ws
Directory Structure
-------------------
[core_root]
|
+-doc Documentation
|
+-bench--+ Test Bench
| +- verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-rtl----+ Core RTL Sources
| +-verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-sim----+
| +-rtl_sim---+ Functional verification Directory
| | +-bin Makefiles/Run Scripts
| | +-run Working Directory
| |
| +-gate_sim--+ Functional & Timing Gate Level
| | Verification Directory
| +-bin Makefiles/Run Scripts
| +-run Working Directory
|
+-lint--+ Lint Directory Tree
| +-bin Makefiles/Run Scripts
| +-run Working Directory
| +-log Linter log & result files
|
+-syn---+ Synthesis Directory Tree
| +-bin Synthesis Scripts
| +-run Working Directory
| +-log Synthesis log files
| +-out Synthesis Output
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