DE2_VGA3
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1246KB
下载次数：93
上传日期：2008-11-11 12:10:21
上 传 者：
boulder
说明： The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
(The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.)
文件列表:
DE2_VGA3\db (0, 2006-06-08)
DE2_VGA3\db\altsyncram_4gp1.tdf (106061, 2006-05-26)
DE2_VGA3\db\altsyncram_a5h1.tdf (2630, 2006-05-26)
DE2_VGA3\db\DE2_Default.(0).cnf.cdb (25308, 2006-06-08)
DE2_VGA3\db\DE2_Default.(0).cnf.hdb (9548, 2006-06-08)
DE2_VGA3\db\DE2_Default.(1).cnf.cdb (1618, 2006-05-26)
DE2_VGA3\db\DE2_Default.(1).cnf.hdb (805, 2006-05-26)
DE2_VGA3\db\DE2_Default.(10).cnf.cdb (12865, 2006-05-26)
DE2_VGA3\db\DE2_Default.(10).cnf.hdb (6232, 2006-05-26)
DE2_VGA3\db\DE2_Default.(11).cnf.cdb (12865, 2006-05-26)
DE2_VGA3\db\DE2_Default.(11).cnf.hdb (6232, 2006-05-26)
DE2_VGA3\db\DE2_Default.(12).cnf.cdb (80598, 2006-05-26)
DE2_VGA3\db\DE2_Default.(12).cnf.hdb (28996, 2006-05-26)
DE2_VGA3\db\DE2_Default.(13).cnf.cdb (11947, 2006-05-26)
DE2_VGA3\db\DE2_Default.(13).cnf.hdb (4091, 2006-05-26)
DE2_VGA3\db\DE2_Default.(2).cnf.cdb (1092, 2006-05-26)
DE2_VGA3\db\DE2_Default.(2).cnf.hdb (578, 2006-05-26)
DE2_VGA3\db\DE2_Default.(3).cnf.cdb (1253, 2006-05-26)
DE2_VGA3\db\DE2_Default.(3).cnf.hdb (736, 2006-05-26)
DE2_VGA3\db\DE2_Default.(4).cnf.cdb (12972, 2006-06-02)
DE2_VGA3\db\DE2_Default.(4).cnf.hdb (2943, 2006-06-02)
DE2_VGA3\db\DE2_Default.(7).cnf.cdb (1396, 2006-05-26)
DE2_VGA3\db\DE2_Default.(7).cnf.hdb (638, 2006-05-26)
DE2_VGA3\db\DE2_Default.(8).cnf.cdb (1287, 2006-05-26)
DE2_VGA3\db\DE2_Default.(8).cnf.hdb (487, 2006-05-26)
DE2_VGA3\db\DE2_Default.asm.qmsg (1623, 2006-06-08)
DE2_VGA3\db\DE2_Default.asm_labs.ddb (479179, 2006-06-08)
DE2_VGA3\db\DE2_Default.cbx.xml (93, 2006-06-08)
DE2_VGA3\db\DE2_Default.cmp.cdb (95760, 2006-06-08)
DE2_VGA3\db\DE2_Default.cmp.hdb (26827, 2006-06-08)
DE2_VGA3\db\DE2_Default.cmp.logdb (4, 2006-06-08)
DE2_VGA3\db\DE2_Default.cmp.qrpt (0, 2006-05-26)
DE2_VGA3\db\DE2_Default.cmp.rdb (59635, 2006-06-08)
DE2_VGA3\db\DE2_Default.cmp.tdb (78597, 2006-06-08)
DE2_VGA3\db\DE2_Default.cmp0.ddb (179208, 2006-06-08)
DE2_VGA3\db\DE2_Default.dbp (0, 2006-06-08)
DE2_VGA3\db\DE2_Default.db_info (135, 2006-05-26)
DE2_VGA3\db\DE2_Default.eco.cdb (140, 2006-06-08)
DE2_VGA3\db\DE2_Default.fit.qmsg (721904, 2006-06-08)
DE2_VGA3\db\DE2_Default.hier_info (32486, 2006-06-08)
... ...
DE2_Default
-----------
This design is the initial design when the board is powered-up. It increments a counter and displays the value on the
7-segment displays and LEDs. An image is also displayed on the VGA port.
Running the Design
------------------
1) Launch the Quartus II software.
2) Open the DE2_Default.qpf project located in the \DE2_Default folder. (File menu -> Open Project)
3) Open the Programmer window. (Tools menu -> Programmer)
4) The DE2_Default.sof programming file should be listed.
Check the 'Program/Configure' box and set up the JTAG programming hardware connection via the 'Hardware Setup' button.
5) Press 'Start' to start programming. The design should now be programmed and running.
User Inputs to the Design
-------------------------
None.
Compiling the Design
--------------------
1) Launch the Quartus II software.
2) Open the DE2_Default.qpf project located in the \DE2_Default folder. (File menu -> Open Project)
3) Start compilation. (Processing -> Start Compilation)
4) After compilation is finished, you can run the design with the generated SOF file. See 'Running the Design' above.
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