an501_design_example
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：279KB
下载次数：21
上传日期：2008-11-21 17:44:09
上 传 者：
1306559
说明： PWM文件
用于CPLD，学习如何用VHDL语言写程序
(PWM files for CPLD, learn how to write VHDL language program)
文件列表:
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example (0, 2007-11-26)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code (0, 2007-11-01)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code\pwm_main.v (4664, 2006-12-27)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim (0, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pulse_width_modulator.cr.mti (1066, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pulse_width_modulator.mpf (17172, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_main.v (4664, 2006-12-27)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_sim.cr.mti (938, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_sim.mpf (9993, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\test_pwm.v (8158, 2006-12-28)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.do (1804, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave2.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave2.do (1618, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave3.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave3.do (1617, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave4.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave4.do (1619, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave5.bmp (248182, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave5.do (1619, 2006-12-29)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work (0, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3 (0, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\verilog.asm (6531, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.dat (850, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.vhd (214, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen (0, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\verilog.asm (3779, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\_primary.dat (341, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\_primary.vhd (217, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen (0, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\verilog.asm (3827, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\_primary.dat (362, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\_primary.vhd (219, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle (0, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\verilog.asm (3674, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\_primary.dat (416, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\_primary.vhd (285, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle (0, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\verilog.asm (3649, 2007-11-05)
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\_primary.dat (420, 2007-11-05)
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