DDR_SDRAM_controller
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：129KB
下载次数：127
上传日期：2008-11-22 13:08:46
上 传 者：
xblpudn
说明： DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.
(DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O )
文件列表:
DDR SDRAM控制器2\ddr_xilinx.pdf (157689, 2007-12-17)
DDR SDRAM控制器2\ddr_verilog_xilinx\define.v (1677, 2000-12-08)
DDR SDRAM控制器2\ddr_verilog_xilinx\glbl.v (109, 2000-10-02)
DDR SDRAM控制器2\ddr_verilog_xilinx\mt46v4m16.v (46857, 2000-12-29)
DDR SDRAM控制器2\ddr_verilog_xilinx\string_decode_fn.v (6858, 2001-01-04)
DDR SDRAM控制器2\ddr_verilog_xilinx\tb_top.v (8248, 2001-01-12)
DDR SDRAM控制器2\ddr_verilog_xilinx\top.ucf (3126, 2001-01-04)
DDR SDRAM控制器2\ddr_verilog_xilinx\top_func.v (45438, 2001-01-12)
DDR SDRAM控制器2\ddr_verilog_xilinx (0, 2008-11-22)
DDR SDRAM控制器2 (0, 2008-11-22)
***********************ReadMe for XAPP253*********************
Contents of xapp253.zip file
contains verilog source files
*top.v* is the source file for DDR SDRAM controller
*tb_top.v* is the source file for testbench
*define.v* contains variable definitions
*mt46v4m16.v* is the simulation model of ***MB DDR SDRAM from Micron
*top.ucf* is the user constraint file to be specified during
Place and Route. This contains the constraints for 133MHz implementation
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