Uartmodule
所属分类：串口编程
开发工具：VHDL
文件大小：39KB
下载次数：31
上传日期：2008-11-27 09:24:51
上 传 者：
ljsu0203
说明： 实现FPGA与PC机的串口通信功能，实现数据的收发。
(FPGA with the realization of PC-serial communication functions to send and receive data.)
文件列表:
Uartmodule\stdout.log (345, 2008-11-26)
Uartmodule\tp.v (3581, 2007-09-19)
Uartmodule\uart_module.cr.mti (1033, 2007-09-20)
Uartmodule\uart_module.mpf (21707, 2007-09-20)
Uartmodule\Uart_rx.v (3702, 2007-09-19)
Uartmodule\Uart_test.v (2202, 2007-09-20)
Uartmodule\Uart_test.v.bak (2202, 2007-09-20)
Uartmodule\uart_top.v (4671, 2007-09-20)
Uartmodule\uart_top.v.bak (4671, 2007-09-20)
Uartmodule\Uart_tx.v (4901, 2007-09-20)
Uartmodule\vish_stacktrace.vstf (27936, 2007-09-20)
Uartmodule\vsim.wlf (32768, 2007-09-20)
Uartmodule\work\@uart_test\verilog.asm (9364, 2007-09-20)
Uartmodule\work\@uart_test\_primary.dat (1101, 2007-09-20)
Uartmodule\work\@uart_test\_primary.vhd (138, 2007-09-20)
Uartmodule\work\uart\verilog.asm (14016, 2007-09-20)
Uartmodule\work\uart\_primary.dat (1942, 2007-09-20)
Uartmodule\work\uart\_primary.vhd (724, 2007-09-20)
Uartmodule\work\uart_rx\verilog.asm (11524, 2007-09-20)
Uartmodule\work\uart_rx\_primary.dat (1874, 2007-09-20)
Uartmodule\work\uart_rx\_primary.vhd (496, 2007-09-20)
Uartmodule\work\uart_tx\verilog.asm (9594, 2007-09-20)
Uartmodule\work\uart_tx\_primary.dat (1700, 2007-09-20)
Uartmodule\work\uart_tx\_primary.vhd (410, 2007-09-20)
Uartmodule\work\_info (970, 2007-09-20)
Uartmodule\work\@uart_test (0, 2008-11-08)
Uartmodule\work\uart (0, 2008-11-08)
Uartmodule\work\uart_rx (0, 2008-11-08)
Uartmodule\work\uart_tx (0, 2008-11-08)
Uartmodule\work (0, 2008-11-08)
Uartmodule (0, 2008-11-08)
近期下载者：
相关文件：
收藏者：