uart
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：218KB
下载次数：135
上传日期：2008-12-03 08:39:49
上 传 者：
litewei
说明： VHDL语言编写的全功能串口模块（包含DTR，RTS等管脚），在CPLD器件上测试通过
(VHDL language, full-featured serial modules (including DTR, RTS pin, etc.), in the CPLD device test)
文件列表:
uart\db\urat.(0).cnf.cdb (8067, 2007-03-23)
uart\db\urat.(0).cnf.hdb (1596, 2007-03-23)
uart\db\urat.asm.qmsg (1592, 2007-03-23)
uart\db\urat.cbx.xml (86, 2007-03-23)
uart\db\urat.cmp.cdb (19695, 2007-03-23)
uart\db\urat.cmp.hdb (7495, 2007-03-23)
uart\db\urat.cmp.kpt (204, 2007-03-23)
uart\db\urat.cmp.logdb (4, 2007-03-23)
uart\db\urat.cmp.rdb (21392, 2007-03-23)
uart\db\urat.cmp.tdb (12862, 2007-03-23)
uart\db\urat.cmp0.ddb (29729, 2007-03-23)
uart\db\urat.dbp (0, 2007-03-23)
uart\db\urat.db_info (135, 2007-03-23)
uart\db\urat.eco.cdb (140, 2007-03-23)
uart\db\urat.eds_overflow (6, 2007-03-23)
uart\db\urat.fit.qmsg (19224, 2007-03-23)
uart\db\urat.hier_info (2057, 2007-03-23)
uart\db\urat.hif (561, 2007-03-23)
uart\db\urat.map.cdb (6392, 2007-03-23)
uart\db\urat.map.hdb (7164, 2007-03-23)
uart\db\urat.map.logdb (4, 2007-03-23)
uart\db\urat.map.qmsg (4217, 2007-03-23)
uart\db\urat.pre_map.cdb (5876, 2007-03-23)
uart\db\urat.pre_map.hdb (7328, 2007-03-23)
uart\db\urat.psp (0, 2007-03-23)
uart\db\urat.rtlv.hdb (7320, 2007-03-23)
uart\db\urat.rtlv_sg.cdb (5825, 2007-03-23)
uart\db\urat.rtlv_sg_swap.cdb (157, 2007-03-23)
uart\db\urat.sgdiff.cdb (7760, 2007-03-23)
uart\db\urat.sgdiff.hdb (7679, 2007-03-23)
uart\db\urat.signalprobe.cdb (678, 2007-03-23)
uart\db\urat.sim.hdb (2345, 2007-03-23)
uart\db\urat.sim.qmsg (3888, 2007-03-23)
uart\db\urat.sim.rdb (3332, 2007-03-23)
uart\db\urat.sim_ori.vwf (30832, 2007-03-23)
uart\db\urat.sld_design_entry.sci (133, 2007-03-23)
uart\db\urat.sld_design_entry_dsc.sci (133, 2007-03-23)
uart\db\urat.syn_hier_info (0, 2007-03-23)
uart\db\urat.tan.qmsg (45208, 2007-03-23)
uart\db\wed.zsf (65, 2007-03-23)
... ...
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