MICO8_DEMO_03_18_08
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3240KB
下载次数：38
上传日期：2008-12-09 11:20:31
上 传 者：
微风清雨
说明： Lattice 超精简8位软核CPU--Mico8，开放所有源代码，包括VHDL，编译器，支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。
(Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to support the GCC compiler. Lattice can all FPGA and MachXO devices use. In this case contains examples and documentation. On the use of Lattice devices users or learning CPU design personnel have a higher reference value.)
文件列表:
Block_Mico8_ECP2_6 (0, 2008-03-21)
Block_Mico8_ECP2_6\.recordref (0, 2008-03-14)
Block_Mico8_ECP2_6\addsub8.naf (349, 2008-03-07)
Block_Mico8_ECP2_6\automake.log (20428, 2008-03-14)
Block_Mico8_ECP2_6\code.mem (10240, 2008-03-10)
Block_Mico8_ECP2_6\code.s (7852, 2008-01-15)
Block_Mico8_ECP2_6\description.txt (2120, 2008-03-14)
Block_Mico8_ECP2_6\DIP8_M8.cmd (512, 2008-01-15)
Block_Mico8_ECP2_6\DIP8_M8.jhd (20, 2008-03-14)
Block_Mico8_ECP2_6\DIP8_M8.naf (257, 2008-03-14)
Block_Mico8_ECP2_6\DIP8_M8.srd (16939, 2008-01-15)
Block_Mico8_ECP2_6\dip8_m8.sym (264, 2008-01-14)
Block_Mico8_ECP2_6\DIP8_M8.szr (8101, 2008-01-15)
Block_Mico8_ECP2_6\DIP8_M8.vhd (3780, 2008-01-15)
Block_Mico8_ECP2_6\dpram16x8.naf (425, 2008-03-07)
Block_Mico8_ECP2_6\dpram32x8.naf (459, 2008-03-07)
Block_Mico8_ECP2_6\INT_Handl_M8.cmd (529, 2008-01-14)
Block_Mico8_ECP2_6\int_handl_m8.jhd (25, 2008-03-14)
Block_Mico8_ECP2_6\INT_Handl_M8.naf (962, 2008-03-14)
Block_Mico8_ECP2_6\INT_Handl_M8.srd (53827, 2008-01-14)
Block_Mico8_ECP2_6\int_handl_m8.sym (648, 2008-01-14)
Block_Mico8_ECP2_6\INT_Handl_M8.szr (8799, 2008-01-14)
Block_Mico8_ECP2_6\int_handl_m8.vhd (9508, 2008-03-13)
Block_Mico8_ECP2_6\INT_Handl_M8_reveal.tcl (465, 2008-01-14)
Block_Mico8_ECP2_6\isp8_alu.jhd (21, 2008-03-14)
Block_Mico8_ECP2_6\isp8_alu.naf (814, 2008-03-14)
Block_Mico8_ECP2_6\isp8_alu.vhd (9464, 2008-03-07)
Block_Mico8_ECP2_6\isp8_cfg5.cmd (596, 2008-03-10)
Block_Mico8_ECP2_6\isp8_cfg5.jhd (66, 2008-03-14)
Block_Mico8_ECP2_6\isp8_cfg5.naf (944, 2008-03-14)
Block_Mico8_ECP2_6\isp8_cfg5.srd (125515, 2008-03-10)
Block_Mico8_ECP2_6\isp8_cfg5.sym (704, 2008-03-10)
Block_Mico8_ECP2_6\isp8_cfg5.szr (10124, 2008-03-10)
Block_Mico8_ECP2_6\isp8_cfg5.vhd (7236, 2008-03-14)
Block_Mico8_ECP2_6\isp8_core.cmd (582, 2008-03-10)
Block_Mico8_ECP2_6\isp8_core.jhd (232, 2008-03-14)
Block_Mico8_ECP2_6\isp8_core.naf (1425, 2008-03-14)
Block_Mico8_ECP2_6\isp8_core.srd (135520, 2008-03-10)
Block_Mico8_ECP2_6\isp8_core.szr (10878, 2008-03-10)
Block_Mico8_ECP2_6\isp8_core.vhd (27085, 2008-03-14)
... ...
Mico8 Demo Features:
- Includes full design & User Guide PowerPoint
- easy Mico8 code storage (supports memory initialisation tool)
- Full Top Level schematic Design
- Block Based peripheral set
- Small size full featured demonstration (350 slices)
- real-world peripheral set
- Example project with code
- Verified and bug-free
The peripheral set:
- TX UART
- 8 LED's (generic 8bit output)
- two 7segment displays
- 8bit PWM
- Character LCD display
- Interrupt controller (4 inputs)
- RX UART
- DIPSwitch (generic 8bit input with interrupt on change)
All of the above is supplied in the demonstration package in source code
VHDL + source assembly code.
The design has been verified in MachXO/EC/ECP/XP.
The design is also an ideal platform to demonstrate Reveal.
I demonstrate the multi-trigger by showing interrupt handling of four peripherals
in a single Reveal run. It uses Mico8 v2.4b (bug fixed version).
The LatticeMico8 microcontroller has also been enhanced to increase the
breadth of embedded applications in which it can be employed. These include
the ability to configure the number of lines of code possible and improved
portability across FPGA architectures. The range of the branch operation has
been increased fourfold to accommodate a larger code space. For improved
support of high-level language compilers, the ability to configure the stack
size has also been introduced.
Notice that the performance of the Mico8 core is much faster due to changing
the addressing (using the top two regs R30/R31 for effectively a Page and stack).
This core will not be code compatible with old cores. Also the interrupt response
was increased slightly, allowing the core to function correctly using
distributed RAM or EBR on all of the families.
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