multi
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：680KB
下载次数：49
上传日期：2008-12-15 00:47:29
上 传 者：
peter_84875466
说明： 基于CPLD/FPGA的十六位乘法器的VHDL实现
(Based on CPLD/FPGA multiplier of 16 to achieve the VHDL)
文件列表:
乘法器\db\add_sub_fjh.tdf (4549, 2008-11-14)
乘法器\db\mul16.(0).cnf.cdb (7249, 2008-11-14)
乘法器\db\mul16.(0).cnf.hdb (1067, 2008-11-14)
乘法器\db\mul16.asm.qmsg (2174, 2008-11-14)
乘法器\db\mul16.asm_labs.ddb (7224, 2008-11-14)
乘法器\db\mul16.cbx.xml (1487, 2008-11-14)
乘法器\db\mul16.cmp.cdb (82611, 2008-11-14)
乘法器\db\mul16.cmp.hdb (17059, 2008-11-14)
乘法器\db\mul16.cmp.logdb (4, 2008-11-14)
乘法器\db\mul16.cmp.rdb (19846, 2008-11-14)
乘法器\db\mul16.cmp.tdb (180094, 2008-11-14)
乘法器\db\mul16.cmp0.ddb (145402, 2008-11-14)
乘法器\db\mul16.db_info (137, 2008-11-14)
乘法器\db\mul16.eco.cdb (161, 2008-11-14)
乘法器\db\mul16.eds_overflow (3, 2008-11-14)
乘法器\db\mul16.fit.qmsg (75160, 2008-11-14)
乘法器\db\mul16.fnsim.cdb (13501, 2008-11-14)
乘法器\db\mul16.fnsim.hdb (30521, 2008-11-14)
乘法器\db\mul16.fnsim.qmsg (15259, 2008-11-14)
乘法器\db\mul16.hier_info (16210, 2008-11-14)
乘法器\db\mul16.hif (751, 2008-11-14)
乘法器\db\mul16.map.cdb (11313, 2008-11-14)
乘法器\db\mul16.map.hdb (14658, 2008-11-14)
乘法器\db\mul16.map.logdb (4, 2008-11-14)
乘法器\db\mul16.map.qmsg (3338, 2008-11-14)
乘法器\db\mul16.pre_map.cdb (4789, 2008-11-14)
乘法器\db\mul16.pre_map.hdb (8523, 2008-11-14)
乘法器\db\mul16.rtlv.hdb (8518, 2008-11-14)
乘法器\db\mul16.rtlv_sg.cdb (4697, 2008-11-14)
乘法器\db\mul16.rtlv_sg_swap.cdb (178, 2008-11-14)
乘法器\db\mul16.sgdiff.cdb (16865, 2008-11-14)
乘法器\db\mul16.sgdiff.hdb (9191, 2008-11-14)
乘法器\db\mul16.signalprobe.cdb (256, 2008-11-14)
乘法器\db\mul16.sim.cvwf (2062, 2008-11-14)
乘法器\db\mul16.sim.hdb (3088, 2008-11-14)
乘法器\db\mul16.sim.qmsg (3298, 2008-11-14)
乘法器\db\mul16.sim.rdb (52803, 2008-11-14)
乘法器\db\mul16.simfam (10, 2008-11-14)
乘法器\db\mul16.sld_design_entry.sci (154, 2008-11-14)
乘法器\db\mul16.sld_design_entry_dsc.sci (154, 2008-11-14)
... ...
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