文件列表:

rtl\CVS\Root (14, 2005-06-07)
rtl\CVS\Repository (8, 2005-06-07)
rtl\CVS\Entries (25, 2005-06-07)
rtl\verilog\CVS\Root (14, 2005-06-07)
rtl\verilog\CVS\Repository (16, 2005-06-07)
rtl\verilog\CVS\Entries (259, 2005-06-07)
rtl\verilog\i2c_master_bit_ctrl.v (17310, 2004-05-07)
rtl\verilog\i2c_master_byte_ctrl.v (10547, 2004-02-18)
rtl\verilog\i2c_master_defines.v (3219, 2001-11-05)
rtl\verilog\i2c_master_top.v (10108, 2005-02-27)
rtl\verilog\timescale.v (23, 2001-09-24)
rtl\vhdl\CVS\Root (14, 2005-06-07)
rtl\vhdl\CVS\Repository (13, 2005-06-07)
rtl\vhdl\CVS\Entries (293, 2005-06-07)
rtl\vhdl\I2C.VHD (13542, 2001-09-24)
rtl\vhdl\i2c_master_bit_ctrl.vhd (18162, 2004-05-07)
rtl\vhdl\i2c_master_byte_ctrl.vhd (12848, 2004-02-18)
rtl\vhdl\i2c_master_top.vhd (13444, 2004-03-14)
rtl\vhdl\tst_ds1621.vhd (6959, 2001-09-24)
rtl\verilog\CVS (0, 2008-11-25)
rtl\vhdl\CVS (0, 2008-11-25)
rtl\CVS (0, 2008-11-25)
rtl\verilog (0, 2008-11-25)
rtl\vhdl (0, 2008-11-25)
rtl (0, 2008-11-25)

-- This code is provided for free and may be used and -- -- distributed without restriction provided that the -- -- copyright statement is not removed from the file and -- -- that any derivative work contains the original -- -- copyright notice and the associated disclaimer. -- -- Comments and suggestions are always welcome -- The i2c_master core consists of three files: - i2c_master_top -- top level - i2c_master_byte_ctrl -- byte controller - i2c_master_bit_ctrl -- bit controller VHDL needs to be compiled in order. The files are listed above in descending order. I2C.VHD and tst_ds1621.vhd are not supported anymore. They remain mostly for historical purposes, altough they might prove usefull. Richard Herveille rherveille@opencores.org

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：