ref-sdr-sdram-vhdl
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：990KB
下载次数：18
上传日期：2008-12-21 09:44:49
上 传 者：
tensorflow2018
说明： 基于VHDL编写的SDR-SDRAM控制器的编程，目前是业界常用的RAM控制器
(VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller)
文件列表:
doc (0, 2000-07-28)
doc\sdr_sdram.pdf (645561, 2000-05-30)
model (0, 2000-07-25)
model\io_utils.vhd (8703, 1998-01-16)
model\mt48lc8m16a2.vhd (62695, 2000-06-06)
model\mt48lc8m16a2.zip (22435, 2000-04-03)
model\mti_pkg.vhd (4305, 1998-08-10)
model\stdlogar.vhd (68654, 1998-01-16)
model\util1164.vhd (3310, 1998-01-16)
route (0, 2000-07-27)
route\pll1.vhd (4718, 2000-06-06)
route\sdr_sdram.csf (3524, 2000-06-06)
route\sdr_sdram.esf (471, 2000-06-06)
route\sdr_sdram.vqm (159152, 2000-06-06)
simulation (0, 2000-07-25)
simulation\APEX20KE_MF.VHD (42676, 2000-06-05)
simulation\io_utils.vhd (8703, 1998-01-16)
simulation\lpm_pack.vhd (22051, 1999-10-22)
simulation\modelsim.ini (8123, 2000-06-06)
simulation\mt48lc8m16a2.vhd (62695, 2000-06-06)
simulation\mti_pkg.vhd (4305, 1998-08-10)
simulation\sdr_sdram_tb.vhd (30112, 2000-06-06)
simulation\stdlogar.vhd (68654, 1998-01-16)
simulation\util1164.vhd (3310, 1998-01-16)
simulation\work (0, 2000-07-25)
simulation\work\altcam (0, 2000-07-25)
simulation\work\altcam\behave.dat (7970, 2000-06-06)
simulation\work\altcam\behave.psm (70000, 2000-06-06)
simulation\work\altcam\_primary.dat (5972, 2000-06-06)
simulation\work\altclklock (0, 2000-07-25)
simulation\work\altclklock\behavior.dat (1975, 2000-06-06)
simulation\work\altclklock\behavior.psm (13536, 2000-06-06)
simulation\work\altclklock\_primary.dat (799, 2000-06-06)
simulation\work\altlvds_rx (0, 2000-07-25)
simulation\work\altlvds_rx\behavior.dat (3122, 2000-06-06)
simulation\work\altlvds_rx\behavior.psm (14960, 2000-06-06)
simulation\work\altlvds_rx\_primary.dat (563, 2000-06-06)
simulation\work\altlvds_tx (0, 2000-07-25)
... ...
SDR SDRAM Controller VHDL Reference Design version 1.1.
This readme files describes the contents of each directory of the SDR SDRAM Controller reference design version 1.1.
File/Directory Description
=============================================================================
\doc SDR SDRAM reference design documentation
\model Contains the vhdl SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation Contains the vhdl testbench, modelsim project file, and library
\source Contains the vhdl source files for the SDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
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