ECCgenAndLoc

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:1469KB
下载次数:90
上传日期:2008-12-21 18:47:55
上 传 者kevin zhuo
说明:  基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序,EccErrLoc文件夹为ECC错误定位程序。
(Xilinx ISE environment based on the development of VHDL the NAND flash ECC to achieve, eccGen256Byte folder produced for the ECC procedures, EccErrLoc folder location for the ECC error procedures.)

文件列表:
eccGen256byte\AutoConstraint_eccGen256byte.sdc (178, 2008-04-14)
eccGen256byte\dist_mem_gen_ds322.pdf (652259, 2008-04-14)
eccGen256byte\dist_mem_gen_release_notes.txt (2918, 2008-04-14)
eccGen256byte\ecc.coe (1085, 2008-04-06)
eccGen256byte\ecc.coe.bak (1064, 2008-04-06)
eccGen256byte\eccGen256byte.cel (0, 2008-04-14)
eccGen256byte\eccgen256byte.cmd_log (3337, 2008-04-14)
eccGen256byte\eccGen256byte.fse (0, 2008-04-14)
eccGen256byte\eccGen256byte.htm (356, 2008-04-14)
eccGen256byte\eccGen256byte.ise (287364, 2008-04-15)
eccGen256byte\eccGen256byte.ise_ISE_Backup (287364, 2008-04-15)
eccGen256byte\eccGen256byte.log (237, 2008-04-14)
eccGen256byte\eccGen256byte.map (0, 2008-04-14)
eccGen256byte\eccGen256byte.ntrc_log (66, 2008-04-11)
eccGen256byte\eccGen256byte.restore (53096, 2008-04-15)
eccGen256byte\eccGen256byte.sap (3873, 2008-04-14)
eccGen256byte\eccGen256byte.sdc (0, 2008-04-06)
eccGen256byte\eccGen256byte.tap (3754, 2008-04-14)
eccGen256byte\eccGen256byte.ucf (1489, 2008-04-14)
eccGen256byte\eccGen256byte.vhd (5867, 2008-04-15)
eccGen256byte\eccGen256byte.vhd.bak (4272, 2008-04-07)
eccGen256byte\eccGen256byte_guide.ncd (29286, 2008-04-11)
eccGen256byte\eccGen256byte_map.map (2794, 2008-04-11)
eccGen256byte\eccGen256byte_summary.html (2311, 2008-04-15)
eccGen256byte\eccgen256byte_summary.xml (408, 2008-04-11)
eccGen256byte\eccTab256.asy (346, 2008-04-14)
eccGen256byte\eccTab256.mif (2560, 2008-04-14)
eccGen256byte\eccTab256.ngc (7247, 2008-04-14)
eccGen256byte\eccTab256.sym (635, 2008-04-14)
eccGen256byte\eccTab256.v (4008, 2008-04-14)
eccGen256byte\eccTab256.veo (2995, 2008-04-14)
eccGen256byte\eccTab256.vhd (4307, 2008-04-14)
eccGen256byte\eccTab256.vho (3408, 2008-04-14)
eccGen256byte\eccTab256.xco (1781, 2008-04-14)
eccGen256byte\eccTab256_flist.txt (214, 2008-04-14)
eccGen256byte\eccTab256_summary.html (2307, 2008-04-14)
eccGen256byte\eccTab256_xmdf.tcl (3198, 2008-04-14)
eccGen256byte\FIFO8x16.asy (787, 2008-04-14)
eccGen256byte\FIFO8x16.ngc (32004, 2008-04-14)
eccGen256byte\FIFO8x16.sym (1347, 2008-04-14)
... ...

The following files were generated for 'FIFO8x16' in directory D:\work\eccGen256byte: FIFO8x16.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. FIFO8x16.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. FIFO8x16.sym: Please see the core data sheet. FIFO8x16.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. FIFO8x16.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. FIFO8x16.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. FIFO8x16.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. FIFO8x16.xco: CORE Generator input file containing the parameters used to regenerate a core. FIFO8x16_fifo_generator_v3_3_xst_1_vhdl.prj: Please see the core data sheet. FIFO8x16_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. FIFO8x16_readme.txt: Text file indicating the files generated and how they are used. FIFO8x16_xmdf.tcl: Please see the core data sheet. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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