c8051
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1054KB
下载次数：27
上传日期：2008-12-22 15:13:58
上 传 者：
thefirstone
说明： USB v1.1 RTL and design specification
文件列表:
doc\c8051_a.pdf (160250, 2001-10-04)
doc\c8051_spec_ok.pdf (451152, 2006-02-23)
doc\c8051.pdf (17358, 2001-02-15)
doc\c8051_spec.pdf (450977, 2001-10-04)
doc\c8051_dsn.pdf (59198, 2001-10-04)
doc\c8051_b.pdf (63831, 2001-10-04)
src_verilog\core\.xhdl3.comp.xref (97809, 2006-09-18)
src_verilog\core\CLOCK_CONTROL_R.v (6047, 2006-09-18)
src_verilog\core\SERIAL_R.v (32138, 2006-09-18)
src_verilog\core\C8051_S.v (25809, 2006-09-18)
src_verilog\core\.xhdl3_data\control_unit.symb (16082, 2006-09-18)
src_verilog\core\.xhdl3_data\ram_sfr_control.code (3235, 2006-09-18)
src_verilog\core\.xhdl3_data\isr.code (2875, 2006-09-18)
src_verilog\core\.xhdl3_data\serial.symb (217008, 2006-09-18)
src_verilog\core\.xhdl3_data\utility.code (17966, 2006-09-18)
src_verilog\core\.xhdl3_data\clock_control.code (2492, 2006-09-18)
src_verilog\core\.xhdl3_data\oci.code (2756, 2006-09-18)
src_verilog\core\.xhdl3_data\ports.symb (18597, 2006-09-18)
src_verilog\core\.xhdl3_data\alu.code (2606, 2006-09-18)
src_verilog\core\.xhdl3_data\timer_0_1.symb (13947, 2006-09-18)
src_verilog\core\.xhdl3_data\oci.symb (13386, 2006-09-18)
src_verilog\core\.xhdl3_data\timer_0_1.code (3253, 2006-09-18)
src_verilog\core\.xhdl3_data\alu.symb (11228, 2006-09-18)
src_verilog\core\.xhdl3_data\control_unit.code (3518, 2006-09-18)
src_verilog\core\.xhdl3_data\memory_control.symb (25012, 2006-09-18)
src_verilog\core\.xhdl3_data\clock_control.symb (7977, 2006-09-18)
src_verilog\core\.xhdl3_data\memory_control.code (3966, 2006-09-18)
src_verilog\core\.xhdl3_data\ports.code (3104, 2006-09-18)
src_verilog\core\.xhdl3_data\serial.code (2617, 2006-09-18)
src_verilog\core\.xhdl3_data\utility.symb (207593, 2006-09-18)
src_verilog\core\.xhdl3_data\c8051.symb (21622, 2006-09-18)
src_verilog\core\.xhdl3_data\c8051.code (3819, 2006-09-18)
src_verilog\core\.xhdl3_data\isr.symb (14691, 2006-09-18)
src_verilog\core\.xhdl3_data\ram_sfr_control.symb (18290, 2006-09-18)
src_verilog\core\TIMER_0_1_R.v (30937, 2006-09-18)
src_verilog\core\ALU_R.v (80501, 2006-09-18)
src_verilog\core\OCI_R.v (9721, 2006-09-18)
src_verilog\core\UTILITY.v (17434, 2006-09-18)
src_verilog\core\PORTS_R.v (9014, 2007-04-24)
src_verilog\core\ISR_R.v (17664, 2006-09-18)
... ...
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