文件列表:

标准U盘.usb (329495, 2005-12-10)
usb2.0 参考设计\usb_funct\bench\CVS\Entries (14, 2001-08-19)
usb2.0 参考设计\usb_funct\bench\CVS\Repository (16, 2001-08-19)
usb2.0 参考设计\usb_funct\bench\CVS\Root (13, 2001-08-19)
usb2.0 参考设计\usb_funct\bench\verilog\CVS\Entries (2, 2001-08-19)
usb2.0 参考设计\usb_funct\bench\verilog\CVS\Repository (24, 2001-08-19)
usb2.0 参考设计\usb_funct\bench\verilog\CVS\Root (13, 2001-08-19)
usb2.0 参考设计\usb_funct\doc\CVS\Entries (135, 2001-08-19)
usb2.0 参考设计\usb_funct\doc\CVS\Repository (14, 2001-08-19)
usb2.0 参考设计\usb_funct\doc\CVS\Root (13, 2001-08-19)
usb2.0 参考设计\usb_funct\doc\STATUS.txt (1573, 2001-08-03)
usb2.0 参考设计\usb_funct\doc\usb_doc.pdf (321938, 2001-08-10)
usb2.0 参考设计\usb_funct\rtl\CVS\Entries (14, 2001-08-19)
usb2.0 参考设计\usb_funct\rtl\CVS\Repository (14, 2001-08-19)
usb2.0 参考设计\usb_funct\rtl\CVS\Root (13, 2001-08-19)
usb2.0 参考设计\usb_funct\rtl\verilog\CVS\Entries (714, 2001-08-19)
usb2.0 参考设计\usb_funct\rtl\verilog\CVS\Repository (22, 2001-08-19)
usb2.0 参考设计\usb_funct\rtl\verilog\CVS\Root (13, 2001-08-19)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_crc16.v (4796, 2001-08-03)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_crc5.v (4159, 2001-08-03)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_defines.v (9328, 2001-08-10)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_ep_rf.v (12004, 2001-08-03)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_ep_rf_dummy.v (5399, 2001-08-03)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_idma.v (12769, 2001-08-03)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_mem_arb.v (5600, 2001-08-03)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_pa.v (8620, 2001-08-10)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_pd.v (12023, 2001-08-10)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_pe.v (27292, 2001-08-10)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_pl.v (13271, 2001-08-10)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_rf.v (49805, 2001-08-10)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_top.v (16897, 2001-08-10)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_utmi_if.v (6551, 2001-08-03)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_utmi_ls.v (16592, 2001-08-10)
usb2.0 参考设计\usb_funct\rtl\verilog\usbf_wb.v (7189, 2001-08-10)
USB是怎么传输数据的，怎么识别设备的（较详细）.doc (663040, 2008-09-18)
usb2.0 参考设计\usb_funct\bench\verilog\CVS (0, 2008-06-16)
usb2.0 参考设计\usb_funct\rtl\verilog\CVS (0, 2008-06-16)
usb2.0 参考设计\usb_funct\bench\CVS (0, 2008-06-16)
usb2.0 参考设计\usb_funct\bench\verilog (0, 2008-06-16)
... ...

The USB 2.0 Function Project Page is: http://www.opencores.org/cores/usb/ To find out more about me (Rudolf Usselmann), please visit: http://www.asics.ws Directory Structure ------------------- [core_root] | +-doc Documentation | +-bench--+ Test Bench | +- verilog Verilog Sources | +-vhdl VHDL Sources | +-rtl----+ Core RTL Sources | +-verilog Verilog Sources | +-vhdl VHDL Sources | +-sim----+ | +-rtl_sim---+ Functional verification Directory | | +-bin Makefiles/Run Scripts | | +-run Working Directory | | | +-gate_sim--+ Functional & Timing Gate Level | | Verification Directory | +-bin Makefiles/Run Scripts | +-run Working Directory | +-lint--+ Lint Directory Tree | +-bin Makefiles/Run Scripts | +-run Working Directory | +-log Linter log & result files | +-syn---+ Synthesis Directory Tree | +-bin Synthesis Scripts | +-run Working Directory | +-log Synthesis log files | +-out Synthesis Output

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