SystemverilogSource
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：486KB
下载次数：77
上传日期：2009-01-09 12:00:37
上 传 者：
finelei2002
说明： systemverilog程序，需要的朋友可以参看
(SystemVerilog procedures need friends can see)
文件列表:
systemverilog程序\fifo_xactn.sv\fifo_xactn.sv (1445, 2007-07-10)
systemverilog程序\fifo_xactn.sv (0, 2008-11-14)
systemverilog程序\lab1\lab1\.solutions\arb_if.v (309, 2005-10-29)
systemverilog程序\lab1\lab1\.solutions\test.v (1512, 2007-07-18)
systemverilog程序\lab1\lab1\.solutions\test.v.bak (1491, 2006-09-14)
systemverilog程序\lab1\lab1\.solutions (0, 2008-11-14)
systemverilog程序\lab1\lab1\hdl\arb.v (1867, 2005-11-05)
systemverilog程序\lab1\lab1\hdl\arb_if.v (135, 2005-10-29)
systemverilog程序\lab1\lab1\hdl\top.v (148, 2005-10-29)
systemverilog程序\lab1\lab1\hdl (0, 2008-11-14)
systemverilog程序\lab1\lab1\Makefile (285, 2005-10-29)
systemverilog程序\lab1\lab1\tests\test.v (613, 2005-11-05)
systemverilog程序\lab1\lab1\tests (0, 2008-11-14)
systemverilog程序\lab1\lab1 (0, 2008-11-14)
systemverilog程序\lab1 (0, 2008-11-14)
systemverilog程序\region\region\Makefile (603, 2006-02-27)
systemverilog程序\region\region\region.sv (2336, 2006-02-27)
systemverilog程序\region\region\sample.sv (1601, 2006-02-27)
systemverilog程序\region\region (0, 2008-11-14)
systemverilog程序\region (0, 2008-11-14)
systemverilog程序\SystemVerilog\snug04_bromley_smith\bus_if\apb.v (8411, 2004-01-28)
systemverilog程序\SystemVerilog\snug04_bromley_smith\bus_if\apb_assertions.v (12311, 2004-02-20)
systemverilog程序\SystemVerilog\snug04_bromley_smith\bus_if\CORDIC_par_seq_APB.v (3817, 2004-01-27)
systemverilog程序\SystemVerilog\snug04_bromley_smith\bus_if\fail.v (957, 2004-02-04)
systemverilog程序\SystemVerilog\snug04_bromley_smith\bus_if (0, 2008-11-14)
systemverilog程序\SystemVerilog\snug04_bromley_smith\common\defs.v (449, 2004-01-16)
systemverilog程序\SystemVerilog\snug04_bromley_smith\common (0, 2008-11-14)
systemverilog程序\SystemVerilog\snug04_bromley_smith\c_model\c_model.c (3638, 2004-01-26)
systemverilog程序\SystemVerilog\snug04_bromley_smith\c_model\c_model.v (445, 2004-01-20)
systemverilog程序\SystemVerilog\snug04_bromley_smith\c_model (0, 2008-11-14)
systemverilog程序\SystemVerilog\snug04_bromley_smith\par_seq\CORDIC_par_seq.v (13568, 2004-02-06)
systemverilog程序\SystemVerilog\snug04_bromley_smith\par_seq (0, 2008-11-14)
systemverilog程序\SystemVerilog\snug04_bromley_smith\snug04_bromley_smith_paper.pdf (105918, 2005-11-14)
systemverilog程序\SystemVerilog\snug04_bromley_smith\snug04_bromley_smith_slides.pdf (399992, 2005-11-14)
systemverilog程序\SystemVerilog\snug04_bromley_smith\Testbench\CORDIC_par_seq_APB_modport_tf.v (1346, 2004-02-18)
systemverilog程序\SystemVerilog\snug04_bromley_smith\Testbench\CORDIC_par_seq_APB_testcase.v (6151, 2004-02-18)
systemverilog程序\SystemVerilog\snug04_bromley_smith\Testbench\CORDIC_par_seq_APB_test_master.v (2964, 2004-02-06)
systemverilog程序\SystemVerilog\snug04_bromley_smith\Testbench\CORDIC_par_seq_APB_test_master_RTL.v (4918, 2004-02-06)
systemverilog程序\SystemVerilog\snug04_bromley_smith\Testbench (0, 2008-11-14)
... ...
This directory contains the source code used in some of the VMM Primer
series. The source code for some VMM Primers can be found in the
examples included in the VMM Open Source distribution.
VMM Primer Title Where?
Writing Command-Layer Master Transactors ./Command_Master_Xactor
Writing Command-Layer Slave Transactors ./Command_Slave_Xactor
Writing Command-Layer Monitors ./Command_Monitor_Xactor
Using the Register Abstraction Layer ./RAL
Composing Environments $VMM_HOME/sv/examples/subenv/oc_ethernet
Using the Data Stream Scoreboard $VMM/sv/examples/sb/apb_bus
Using the Memory Allocation Manager $VMM_HOME/sv/examples/subenv/oc_ethernet
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