文件列表:

sv-design_book_examples\chapter_02\02.02.00_snippet-1.sv (1941, 2004-07-27)
sv-design_book_examples\chapter_02\02.02.00_snippet-2.sv (1805, 2004-07-27)
sv-design_book_examples\chapter_02\02.02.00_snippet-3.sv (1935, 2004-07-27)
sv-design_book_examples\chapter_02\02.03.00_example_2-1.sv (2935, 2004-07-27)
sv-design_book_examples\chapter_02\02.03.03_snippet-1.sv (2139, 2004-07-27)
sv-design_book_examples\chapter_02\02.04.04_example_2-2.sv (3849, 2004-07-27)
sv-design_book_examples\chapter_02\02.06.00_example_2-3.sv (2220, 2004-07-27)
sv-design_book_examples\chapter_02\02.06.00_example_2-4.sv (2869, 2004-07-27)
sv-design_book_examples\chapter_02\02.08.00_snippet-1.sv (2564, 2004-07-27)
sv-design_book_examples\chapter_02\02.08.00_snippet-2.sv (2173, 2004-07-27)
sv-design_book_examples\chapter_02\02.08.00_snippet-3.sv (2362, 2004-07-27)
sv-design_book_examples\chapter_02\02.09.01_snippet-1.sv (2750, 2004-07-27)
sv-design_book_examples\chapter_02\02.09.02_example_2-5.sv (2415, 2004-07-27)
sv-design_book_examples\chapter_02\02.11.00_snippet-1.sv (2090, 2004-07-27)
sv-design_book_examples\chapter_02\02.11.00_snippet-2.sv (2313, 2004-07-27)
sv-design_book_examples\chapter_02 (0, 2009-01-06)
sv-design_book_examples\chapter_03\03.01.00_snippet-1.sv (2105, 2004-07-27)
sv-design_book_examples\chapter_03\03.01.01_snippet-1.sv (1934, 2004-07-27)
sv-design_book_examples\chapter_03\03.01.02_example_3-1.sv (3147, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.00_example_3-2.v (3118, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.00_example_3-3.sv (2982, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.01_snippet-1.sv (1878, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.02_snippet-1.sv (2067, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.03_snippet-1.sv (1951, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.03_snippet-2.sv (2000, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.03_snippet-3.sv (1968, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.03_snippet-4.sv (1976, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.04_snippet-1.sv (1866, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.04_snippet-2.sv (1951, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.04_snippet-3.sv (1975, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.04_snippet-4.sv (1980, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.04_snippet-5.sv (1848, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.04_snippet-6.sv (1929, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.06_snippet-1.sv (2005, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.06_snippet-2.sv (1950, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.06_snippet-3.sv (1936, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.06_snippet-4.sv (1945, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.06_snippet-5.sv (1957, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.07_snippet-1.sv (2371, 2004-07-27)
sv-design_book_examples\chapter_03\03.02.08_example_3-4.sv (4171, 2004-07-27)
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26 Jul 2004 This directory contains code examples and snippets from the book "SystemVerilog for Design", by Stuart Sutherland, Simon Davidmann, and Peter Flake. Book copyright: 2003, Kluwer Academic Publishers, Norwell, MA, USA www.wkap.il, ISBN: 0-4020-7530-8. The examples are provided as a courtesy to readers of the book who wish to try out the examples. Each example includes a bare bones test in order to verify that the example compiles, loads and runs in simulation. The rudimentary tests are NOT comprehensive, and are NOT intended to be used to verify proper implementation of SystemVerilog by software tools. The intent of the simple tests is to show the that each example is syntactically and semantically correct. All examples are copyrighted by Sutherland HDL, Inc. The examples may be used and distributed without restriction, provided that the entire comment block of each example is included with the example. CAVEATS: a) These examples are a subset of SystemVerilog, focussing on the extensions to Verilog that either are synthesizable, or are expected to be synthesizable, using current RTL synthesis technologies. b) The examples are NOT intended to be a validation suite for SystemVerilog tools. The examples are only meant to illustrate how specific SystemVerilog features might be used. c) Some of examples are not fully tested, as the examples were developed before EDA tools were available to verify all examples. d) The examples include rudimentary test code for use with simulation tools. Some modification to the examples may be required in order to try the examples with other types of tools, such as conditionally removing the test code for synthesis compilers. e) Simulation results and expected results are displayed for visual verification. The rudimentary tests do not include automated self-checking. f) The expected results of the examples are based on the author's interpretation of the SystemVerilog standard. There are currently no SystemVerilog validation suites with which to verify that the expected results are correct. ERRATA: A list of known errata in the book and book examples is available at www.sutherland-hdl.com REPORTING ERRORS OR SUGGESTIONS: The book authors would like to hear about any problems or errors you encounter with these examples. Suggestions on how to improve any examples are also welcome. Please send your feedback to: Stuart Sutherland stuart@sutherland-hdl.com

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