文件列表:

watchver\cnt60.v (474, 2006-11-29)
watchver\core.tpl (1486, 2006-11-29)
watchver\dcm1.v (2198, 2006-11-29)
watchver\dcm1.xaw (2833, 2006-11-29)
watchver\dcm1_arwz.ucf (629, 2006-11-29)
watchver\decode.v (659, 2006-11-29)
watchver\hex2led.v (802, 2006-11-29)
watchver\smallcntr.v (322, 2006-11-29)
watchver\statmach.v (1821, 2006-11-29)
watchver\stopwatch.v (1198, 2006-11-29)
watchver\stopwatch.vcd (246490, 2006-11-29)
watchver\stopwatch_tb.tf (756, 2006-11-29)
watchver\stopwatch_tb.v (2026, 2006-11-29)
watchver\stopwatch_tb_timing.tf (1029, 2006-11-29)
watchver\tenths.edn (16331, 2006-11-29)
watchver\tenths.v (4141, 2006-11-29)
watchver\tenths.veo (2946, 2006-11-29)
watchver\tenths.xco (1691, 2006-11-29)
watchver\watch_ver.ise (223892, 2006-11-29)

-- Copyright(C) 2006 by Xilinx, Inc. All rights reserved. -- The files included in this design directory contain proprietary, confidential information of -- Xilinx, Inc., are distributed under license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid license agreement with Xilinx, Inc. -- This copyright notice must be retained as part of this text at all times. WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip 2Vp2 FG256 -7) CONTROLS Inputs: * CLK -System clock for the Watch design. * STRTSTOP -Starts and stops the stoopwatch. This is an active-low signal which acts like the start/stop button on a runner's stop-watch. * RESET -Resets the stopwatch to 00.0 after it has been stopped. Outputs: * TENSOUT[6:0] -7-bit bus which represents the Tens digit of the stopwatch value. This bus is in 7-segment display format to be viewable on the 7-segment LED display. * ONESOUT[6:0] -similar to TENSOUT bus above, but represents the Ones digit of the stopwatch value. * TENTHSOUT[9:0] -10-bit bus which represents the Tenths digit of the stopwatch value. This bus is one-hot encoded. DESCRIPTION: * STOPWATCH -Top level HDL file. * STMACH_V -State Machine macro. * CNT60 -Verilog module which counts from 0 to 59, decimal. This macro has two 4-bit outputs, which represent the 'ones' and 'tens' digits of the decimal values, respectively. * DCM1 -A single DCM clocking module created with Xilinx Architecture Wizard. * DECODE -HDL-based macro. This macro converts a binary input to a one-hot output. * TENTHS -A Coregen 10-bit, one-hot encoded counter. This macro outputs the 'tenths' digit of the watch value as a 10-bit one-hot encoded value. * HEX2LED -HDL-based macro. This macro decodes the ones and tens digit values from hexadecimal to 7-segment display format. SIMULATION: Behavioural and RTL Simulation done using Verilog Testbench (stopwatch_tb.v). Documentation ------------- Refer to the ISE indepth tutorial available at: http://www.xilinx.com/support/techsup/tutorials/index.htm For support information and contacts please see: http://www.xilinx.com/support or http://www.xilinx.com/support/services/contact_info.htm

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