文件列表:

sdram_ver_134\brst_cntr.v (1409, 2006-11-15)
sdram_ver_134\cslt_cntr.v (1330, 2006-11-15)
sdram_ver_134\define.v (759, 2006-11-15)
sdram_ver_134\ki_cntr.v (1299, 2006-11-15)
sdram_ver_134\micron\bank0.txt (150, 2006-11-15)
sdram_ver_134\micron\bank1.txt (150, 2006-11-15)
sdram_ver_134\micron\mt48lc1m16a1-8a.v (35448, 2006-11-15)
sdram_ver_134\micron\mt48lc1m16a1.v (35485, 2006-11-15)
sdram_ver_134\micron\test.v (31992, 2006-11-15)
sdram_ver_134\rcd_cntr.v (1327, 2006-11-15)
sdram_ver_134\ref_cntr.v (1423, 2006-11-15)
sdram_ver_134\sdram_ver_134.ise (228402, 2006-11-15)
sdram_ver_134\sdrm.ucf (40, 2006-11-15)
sdram_ver_134\sdrm.v (14366, 2006-11-15)
sdram_ver_134\sdrmc_state.v (6150, 2006-11-15)
sdram_ver_134\sdrm_t.v (5051, 2006-11-15)
sdram_ver_134\string_decode_fn.v (5742, 2006-11-15)
sdram_ver_134\string_decode_post_route.v (1709, 2006-11-15)
sdram_ver_134\sys_int.v (7861, 2006-11-15)
sdram_ver_134\tb_post_route.tf (8469, 2006-11-15)
sdram_ver_134\tb_sdrm.tf (8298, 2006-11-15)

-- Copyright(C) 2006 by Xilinx, Inc. All rights reserved. -- The files included in this design directory contain proprietary, confidential information of -- Xilinx, Inc., are distributed under license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid license agreement with Xilinx, Inc. -- This copyright notice must be retained as part of this text at all times. Design Description: The SDRAM controller was originally designed for a Virtex device. It's simulated with Micron SDRAM models. The design is verified with backannotated simulation at 100MHz. For a full functional description see Application Note 134: http://www.xilinx.com/xapp/xapp134.pdf Design Type: ISE (chip 4VSX25 FF668 -12) Design Hierarchy: sdrm (top level) tb_sdrm.tf (Test Bench) sys_int (system interface) sdrm_t (SDRAM controller) sdrmc_state (state machine) brst_cntr (burst counter) rcd_cntr (ras-cas-delay counter) ref_cntr (refresh counter) cslt_cntr (cas-latency counter) ki_cntr (keep-idle-during-refresh-active counter) Simulation: Requires the following simulation libraries: Unisims Simprims Warning: The File->Save Project As... operation of Project Navigator does not copy files included with the `include statement. If this example is saved to a new location, the user should manually copy the following files to the new location. For synthesis: define.v For Simulation: micron folder, string_decode_fn.v and string_decode_post_route.v Design Notes: - DLL: (in sdrm module) . dll0: use for clock mirror, provide the clock for the external SDRAM . dll1: use for deskewing clock signal inside the FPGA (Clk_j), also provide clk2x (Clk_i) - Use global clock buffers for clock signals: . There are 4 BUFGPs in Virtex. They provide low-skew high-fanout routings. - Use LUT Shift Register to delay signals by certain number of clock cycles . delay DLL lock signal (in sdrm_t module) . delay data (in sys_int module) - Registering all inputs and ouputs to SDRAM: (in sdrm module) . All signals going to the SDRAM are registered in the IOB This makes it easy to calculate timings b/t the FPGA and SDRAM For write cycles, add FPGA Tiockp to SDRAM Tsu For read cycles, add SDRAM Tac to FPGA Tsu and . The tristate signal for the data lines are also registered in the IOB . Instead of 1 tristate signal for the Data lines, we duplicate it to 4 signals, each having 8 loads. This was done to reduce net delays on that tristate signal. The tristate signal is sd_doe_n in sdrm - Use fast output buffers: (in sdrm module) . IOBUF_F_12: all signals interfacing to SDRAM These may create more bounce but are ~2ns faster than regular OBUFs - Use NODELAY mode for input buffers: (in ucf constraint file) . The default IBUF has additional delay to give negative hold time. This eliminates pad-to-pad hold time . Set NODELAY attribute on inputs to reduce IBUF delay by about 1.5ns - Set timing constraints for place & route tool: (in ucf constraint file) . set clock period on input clock (Clkp) . set periods b/t clk1x and clk2x (Clk_j, Clk_i) . set OFFSET constraint for inputs and outputs Frequently asked questions: 1. Is RAS to CAS delay programmable? . No, the data registers has a fixed number of pipeline stages. This reference design supports RAS-to-CAS delay of 2 clock cycles. If you need to adjust to a different RAS-to-CAS delay, change the SRL16 Address values in sys_int.v. The address value should be (Trcd/Tck) +1 . Note, you still need to write the RAS-to-CAS value to the Controller's Mode Reg during PRECHARGE command. The value should be (Trcd/Tck) -2 2. How do I modify the design to support 128Mb/256Mb SDRAM parts with a ***-bit data bus? . You'll need to add more IO buffers for the extra data and address signals (in sdrm.v) . You'll need to change ADDR_MSB and DATA_MSB (in define.v) . In the current design, instead of 1 tristate signal for the Data lines, we duplicate it to 4 signals, each having 8 loads. This was done to reduce net delays on that tristate signal. You may need to add 4 more tristate lines if you're going to ***-bit. The tristate signal is sd_doe_n in sdrm.v NOTE: If you are trying to run this example in a read-only location, the design hierachy will not display properly. Please copy the example project to a new location by using either Project Save As... from the File menu pulldown in ISE or some other method of your choice. Copy the example to a location where you have write permissions and the hiearchy will display properly. For support information and contacts please see: http://www.xilinx.com/support or http://www.xilinx.com/support/services/contact_info.htm

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