文件列表:

pn_gen_vhd_211\iq_pn_gen.vhd (7826, 2006-11-15)
pn_gen_vhd_211\pni_gold.dat (262142, 2006-11-15)
pn_gen_vhd_211\pnq_gold.dat (393213, 2006-11-15)
pn_gen_vhd_211\pn_gen_srl_test.vhd (1177, 2006-11-15)
pn_gen_vhd_211\pn_gen_vhd_211.ise (214423, 2006-11-15)

-- Copyright(C) 2006 by Xilinx, Inc. All rights reserved. -- The files included in this design directory contain proprietary, confidential information of -- Xilinx, Inc., are distributed under license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid license agreement with Xilinx, Inc. -- This copyright notice must be retained as part of this text at all times. Design Description: PN Generator Using the Virtex5 SRL Macro. This design is based on XAPP 211. For a full functional description see Application Note 211: http://www.xilinx.com/xapp/xapp211.pdf Design Type: ISE (chip 5VLX50 FF324 -3) Source File: pn_gen_srl_test.vhd - Top-level, self-checking test bench that instantiates the pn generator. iq_pn_gen.vhd - VHDL RTL version of pn generator code. pni_gold.dat - "Golden" I channel data used by the test bench to compare against actual pn sequence generated by the design. pnq_gold.dat - "Golden" Q channel data used by the test bench to compare against actual pn sequence generated by the design. Synthesis: Comments are provided in the verilog (iq_pn_gen.v) PN generator RTL code that indicate what parameters are available to customize the implementation. The number of taps are fixed however the tap points and LFSR width are parameratizable. The code provides a `define compiler directive that can be used to steer the code to infer Flip-flops instead of SRL16E elements. This can be useful allowing the code to be written such that it takes advantage of the SRL16Es when targetting Virtex based devices, but also allows for easy portability to other non-Virtex technologies. Simulation: Requires the following simulation libraries: Unisims Simprims Using ModelSim, compile the pn_gen_srl_test.v and either the verilog version (iq_pn_gen.v) or VHDL version (iq_pn_gen.vhd) of the pn generator. The clock period is set in the test bench for 10ns. The example LFSRs in the code have a length of 17 bits wide therefore they will produce a pn sequence 2^^17 - 1 bits long (before repeating). Run the simulation for approximately 1.32 ms to simulate the entire sequence. (At a 10 ns clock period, the entire sequence will take 1,310,710 ns.) The test bench is self-checking and will compare the output of the I channel LFSR and Q channel LFSR with "golden" data from the pni_gold.dat and pnq_gold.dat files, respectively. Each bit comparison is reported in the command window showing the simulation time, the golden bit value, and the actual bit value. If there's a mismatch between the two bits, the simluation will stop. The test bench will also produce two files containing the actual bits generated. Bits generated from the I channel LFSR will be written in a file called pni_testout.dat, and bits generated from the Q channel LFSR will be written in a file called pnq_testout.dat. NOTE: If you are trying to run this example in a read-only location, the design hierachy will not display properly. Please copy the example project to a new location by using either Project Save As... from the File menu pulldown in ISE or some other method of your choice. Copy the example to a location where you have write permissions and the hiearchy will display properly. For support information and contacts please see: http://www.xilinx.com/support or http://www.xilinx.com/support/services/contact_info.htm

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：