AlteraSDR-SDRAM
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：792KB
下载次数：561
上传日期：2009-02-22 08:40:05
上 传 者：
machenghai
说明： Altera 官方提供的SDRAM控制器,verilog的
(SDRAM controller provided by Altera in Verilog HDL)
文件列表:
doc (0, 2000-07-28)
doc\sdr_sdram.pdf (645561, 2000-05-30)
model (0, 2000-07-25)
model\mt48lc8m16a2.v (43832, 2000-05-23)
route (0, 2000-07-28)
route\PLL1.v (4647, 2000-05-22)
route\sdr_sdram.csf (3524, 2000-07-25)
route\sdr_sdram.esf (471, 2000-07-25)
route\sdr_sdram.vqm (164902, 2000-07-12)
simulation (0, 2000-07-25)
simulation\modelsim.ini (7728, 2000-05-19)
simulation\sdr_sdram_tb.v (22444, 2000-07-12)
simulation\work (0, 2000-07-25)
simulation\work\altclklock (0, 2000-07-25)
simulation\work\altclklock\verilog.psm (20672, 2000-05-23)
simulation\work\altclklock\_primary.dat (2337, 2000-05-23)
simulation\work\altclklock\_primary.vhd (898, 2000-05-23)
simulation\work\command (0, 2000-07-25)
simulation\work\command\verilog.psm (47616, 2000-07-12)
simulation\work\command\_primary.dat (5388, 2000-07-12)
simulation\work\command\_primary.vhd (1319, 2000-07-12)
simulation\work\control_interface (0, 2000-07-25)
simulation\work\control_interface\verilog.psm (21576, 2000-05-23)
simulation\work\control_interface\_primary.dat (2751, 2000-05-23)
simulation\work\control_interface\_primary.vhd (1105, 2000-05-23)
simulation\work\mt48lc8m16a2 (0, 2000-07-25)
simulation\work\mt48lc8m16a2\verilog.psm (240800, 2000-05-23)
simulation\work\mt48lc8m16a2\_primary.dat (24807, 2000-05-23)
simulation\work\mt48lc8m16a2\_primary.vhd (1291, 2000-05-23)
simulation\work\pll1 (0, 2000-07-25)
simulation\work\pll1\verilog.psm (4872, 2000-05-23)
simulation\work\pll1\_primary.dat (827, 2000-05-23)
simulation\work\pll1\_primary.vhd (256, 2000-05-23)
simulation\work\sdr_data_path (0, 2000-07-25)
simulation\work\sdr_data_path\verilog.psm (5704, 2000-05-23)
simulation\work\sdr_data_path\_primary.dat (984, 2000-05-23)
simulation\work\sdr_data_path\_primary.vhd (607, 2000-05-23)
simulation\work\sdr_sdram (0, 2000-07-25)
... ...
SDR SDRAM Controller Verilog Reference Design version 1.1.
This readme files describes the contents of each directory of the SDR SDRAM Controller reference design version 1.1 and
the new feature in the current version.
File/Directory Description
=============================================================================
\doc SDR SDRAM reference design documentation
\model Contains the verilog SDRAM model
\route Contains the Quartus 2000.05 project files for the controller design.
\simulation Contains the verilog testbench, modelsim project file, and library
\source Contains the verilog source files for the SDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
New Feature in SDR SDRAM Controller Verilog Reference Design version 1.1
=============================================================================
The SDR SDRAM Controller Reference Design version 1.1 issues a Burst terminate command to the SDRAM device when the device is
in Page Mode operation. In a Page Mode operation, in order to terminate the burst transfer, the user needs to issue a
precharge command as described in the \doc\SDR_SDRAM.pdf. The controller will then issue a Burst Terminate command to
the SDRAM device. In the previous version, the SDR SDRAM controller will issue a precharge to the SDRAM device in order to stop the burst.
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