uart8
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：856KB
下载次数：141
上传日期：2009-03-08 17:06:20
上 传 者：
jackiee
说明： 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。
(Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.)
文件列表:
uart8 (0, 2009-01-08)
uart8\component (0, 2008-09-11)
uart8\component\Actel (0, 2008-09-11)
uart8\component\Actel\DirectCore (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103 (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\coreparameters.v (368, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\COREUART.cxf (1874, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\mti (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\mti\lib_vlog_obs (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\mti\lib_vlog_obs\COREUART_LIB (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\mti\lib_vlog_obs\COREUART_LIB\_info (96, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\mti\scripts (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\mti\scripts\wave_vlog.do (1458, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog\core_obfuscated (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog\core_obfuscated\Clock_gen.v (1660, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog\core_obfuscated\CoreUART.v (6766, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog\core_obfuscated\fifo_256x8_pa3.v (3293, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog\core_obfuscated\Rx_async.v (8079, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog\core_obfuscated\Tx_async.v (5169, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog\test (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog\test\verif (0, 2008-09-11)
uart8\component\Actel\DirectCore\COREUART\3.1.103\rtl\vlog\test\verif\testbnch.v (33061, 2008-09-11)
uart8\component\work (0, 2008-09-11)
uart8\component\work\UartIP (0, 2008-09-11)
uart8\component\work\UartIP\testbench.v (1506, 2008-09-11)
uart8\component\work\UartIP\UartIP.cxf (4424, 2008-09-11)
uart8\component\work\UartIP\UartIP.sdb (14336, 2008-09-11)
uart8\component\work\UartIP\UartIP.v (1467, 2008-09-11)
uart8\constraint (0, 2008-09-11)
uart8\constraint\uart_ctrl.sdc (1417, 2008-09-15)
uart8\coreconsole (0, 2008-09-11)
uart8\coreconsole\UartIP (0, 2008-09-11)
uart8\designer (0, 2008-09-11)
uart8\designer\impl1 (0, 2009-01-09)
uart8\designer\impl1\designer.log (9673, 2009-01-09)
uart8\designer\impl1\designer_genhdl.log (1164, 2009-01-08)
uart8\designer\impl1\PLL_1536.ide_des (187, 2008-09-13)
... ...
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